32 research outputs found

    Electrical and physical characterization of the Al<sub>2</sub>O<sub>3</sub>/ <i>p</i>-GaSb interface for 1%, 5%, 10%, and 22% (NH<sub>4</sub>)<sub>2</sub>S surface treatments

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    In this work, the impact of ammonium sulfide ((NH&lt;sub&gt;4&lt;/sub&gt;)&lt;sub&gt;2&lt;/sub&gt;S) surface treatment on the electrical passivation of the Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;/ &lt;i&gt;p&lt;/i&gt;-GaSb interface is studied for varying sulfide concentrations. Prior to atomic layer deposition of Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;, GaSb surfaces were treated in 1%, 5%, 10%, and 22% (NH&lt;sub&gt;4&lt;/sub&gt;)&lt;sub&gt;2&lt;/sub&gt;S solutions for 10 min at 295 K. The smallest stretch-out and flatband voltage shifts coupled with the largest capacitance swing, as indicated by capacitance-voltage (&lt;i&gt;CV&lt;/i&gt;) measurements, were obtained for the 1% treatment. The resulting interface defect trap density (&lt;i&gt;D&lt;/i&gt;&lt;sub&gt;it&lt;/sub&gt;) distribution showed a minimum value of 4 x 10&lt;sup&gt;12&lt;/sup&gt; cm&lt;sup&gt;-2&lt;/sup&gt;eV&lt;sup&gt;-1&lt;/sup&gt; at &lt;i&gt;E&lt;/i&gt;&lt;sub&gt;v&lt;/sub&gt; + 0.27 eV. Transmission electron microscopy and atomic force microscopy examination revealed the formation of interfacial layers and increased roughness at the Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;/ &lt;i&gt;p&lt;/i&gt;-GaSb interface of samples treated with 10% and 22% (NH&lt;sub&gt;4&lt;/sub&gt;)&lt;sub&gt;2&lt;/sub&gt;S. In combination, these effects degrade the interface quality as reflected in the &lt;i&gt;CV&lt;/i&gt; characteristics

    (Invited) towards a vertical and damage free post-etch InGaAs fin profile: dry etch processing, sidewall damage assessment and mitigation options

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    Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins

    The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors

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    This study reports the impact of forming gas annealing (FGA) on the electrical characteristics of sulfur passivated, atomic layer deposited Al2O3 gate dielectrics deposited on (110) oriented n- and p-doped In0.53Ga0.47 As layers metal-oxide-semiconductor capacitors (MOSCAPs). In combination, these approaches enable significant Fermi level movement through the bandgap of both n- and p-doped In0.53Ga0.47 As (110) MOSCAPs. A midgap interface trap density (Dit) value in the range 0.87−1.8×1012 cm−2eV−10.87−1.8×1012 cm−2eV−1 is observed from the samples studied. Close to the conduction band edge, a Dit value of 3.1×1011 cm−2eV−13.1×1011 cm−2eV−1 is obtained. These data indicate the combination of sulfur pre-treatment and FGA is advantageous in passivating trap states in the upper half of the bandgap of (110) oriented In0.53Ga0.47 As. This is further demonstrated by a reduction in border trap density in the n-type In0.53Ga0.47 As (110) MOSCAPs from 1.8×1012 cm−21.8×1012 cm−2 to 5.3×1011 cm−25.3×1011 cm−2 as a result of the FGA process. This is in contrast to the observed increase in border trap density after FGA from 7.3×1011 cm−27.3×1011 cm−2 to 1.4×1012 cm−21.4×1012 cm−2 in p-type In0.53Ga0.47 As (110) MOSCAPs, which suggest FGA is not as effective in passsivating states close to the valence band edge

    Characterization of VO 2

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    Suitability Study of Oxide/Gallium Arsenide Interfaces for MOSFET Applications

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    InGaAs (110) Surface Cleaning Using Atomic Hydrogen

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    Enhancement-Mode GaAs n-Channel MOSFET

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    Magnetic Field Sensor Based on Varistor Response

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