Peeling back the layers: Deconstructing information literacy discourse in higher education

The discourses of information literacy practice create epistemological assumptions about how the practice should happen, who should be responsible and under what conditions instruction should be given. Analysis of a wide range of documents and texts emerging from the Higher Education (HE) sector suggest that information literacy (IL) is shaped by two competing and incongruent narratives. The outward facing narrative of information literacy (located in information literacy standards and guidelines) positions information literacy as an empowering practice that arms students with the knowledge and skills to battle the complexity of the modern information world. In contrast, the inward facing narrative (located in information literacy texts) positions students as lacking appropriate knowledge, skills and agency. This deficit perception, which has the capacity to influence pedagogical practice, is at odds with constructivist and action-oriented views that are espoused within information literacy instructional pedagogy. This presentation represents the first paper in a research programme that interrogates the epistemological premises and discourses of information literacy within HE

The global subject of precarity

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Stateful Three-Input Logic with Memristive Switches

Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation