Asynchronous front-end asic for x-ray medical imaging applications implemented in CMOS 0.18μm technology

An idea as well as a CMOS implementation of the novel multi-channel readout front-end ASIC for nuclear X-ray imaging system has been presented in the paper. The circuit has been designed in an example configuration with eight equal channels, but the modular structure enables an easy realization of larger systems with even hundreds of channels. Various new circuit solutions have been proposed by author and used in the circuit, such as: an asynchronous output multiplexer, a pulse shaper and a peak detector with a built-in clock generator, which activates the circuit only in the situation when a new impulse occurs at the input. This technique allows for very low power dissipation. In the worst case scenario, i.e. when all channels would be active at the same time, the power dissipation is kept below 2 mW. By introducing an efficient RESET mechanism that turns off a given channel just after reading out the information, the counting rate of a single channel has been increased to about 3 MSps. The proposed circuit solutions allow for a very low chip area usage that for a single channel is equal to 0.021 mm2, while the total chip area is equal to 0.17 mm2

PARALLEL MATRIX MULTIPLICATION CIRCUITS FOR USE IN KALMAN FILTERING

In this work we propose several ways of the CMOS implementation of a circuit for the multiplication of matrices. We mainly focus on parallel and asynchronous solutions, however serial and mixed approaches are also discussed for the comparison. Practical applications are the motivation behind our investigations. They include fast Kalman filtering commonly used in automotive active safety functions, for example. In such filters, numerous time-consuming operations on matrices are performed. An additional problem is the growing amount of data to be processed. It results from the growing number of sensors in the vehicle as fully autonomous driving is developed. Software solutions may prove themselves to be insuffucient in the nearest future. That is why hardware coprocessors are in the area of our interests as they could take over some of the most time-consuming operations. The paper presents possible solutions, tailored to specific problems (sizes of multiplied matrices, number of bits in signals, etc.). The estimates of the performance made on the basis of selected simulation and measurement results show that multiplication of 3×3 matrices with data rate of 20 100 MSps is achievable in the CMOS 130 nm technology

NOVEL, LOW POWER, NONLINEAR DILATATION AND EROSION FILTERS REALIZED IN THE CMOS TECHNOLOGY

In this paper we propose novel, binary-tree, asynchronous, nonlinear filters suitable for signal processing realized at the transistor level. Two versions of the filter have been proposed, namely the dilatation (Max) and the erosion (Min) one. In the proposed circuits an input signal (current) is sampled in a delay line, controlled by a multiphase clock. In the subsequent stage particular samples are converted to 1-bit digital signals with delays proportional to the values of these samples. In the last step the delays are compared in digital binary-tree structure in order to find either the Min or the Max value, depending on which filter is used. Both circuits have been simulated in the TSMC CMOS 0.18μm technology. To make the results reliable we applied the corner analysis procedure. The circuits were tested for temperatures ranging from -40 to 120ºC, for different transistor models and supply voltages. The circuits offer a precision of about 99% at a typical detection time of 20 ns (for the Max filter) and 100 ns for the Min filter (the worst case scenario). The energy consumed per one input during a single calculation cycle equals 0.32 and 1.57 pJ, for the Max and Min filters, respectively

A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip

An efficient transistor level implementation of a flexible, programmable Triangular Function (TF) that can be used as a Triangular Neighborhood Function (TNF) in ultra-low power, self-organizing maps (SOMs) realized as Application-Specific Integrated Circuit (ASIC) is presented. The proposed TNF block is a component of a larger neighborhood mechanism, whose role is to determine the distance between the winning neuron and all neighboring neurons. Detailed simulations carried out for the software model of such network show that the TNF forms a good approximation of the Gaussian Neighborhood Function (GNF), while being implemented in a much easier way in hardware. The overall mechanism is very fast. In the CMOS 0.18 mu m technology, distances to all neighboring neurons are determined in parallel, within the time not exceeding 11 ns, for an example neighborhood range, R, of 15. The TNF blocks in particular neurons require another 6 ns to calculate the output values directly used in the adaptation process. This is also performed in parallel in all neurons. As a result, after determining the winning neuron, the entire map is ready for the adaptation after the time not exceeding 17 ns, even for large numbers of neurons. This feature allows for the realization of ultra low power SOMs, which are hundred times faster than similar SOMs realized on PC. The signal resolution at the output of the TNF block has a dominant impact on the overall energy consumption as well as the silicon area. Detailed system level simulations of the SOM show that even for low resolutions of 3 to 6 bits, the learning abilities of the SUM are not affected. The circuit performance has been verified by means of transistor level Hspice simulations carried out for different transistor models and different values of supply voltage and the environment temperature - a typical procedure completed in case of commercial chips that makes the obtained results reliable. (C) 2011 Elsevier Ltd. All rights reserved

A Flexible, Low-Power, Programmable Unsupervised Neural Network Based on Microcontrollers for Medical Applications

We present an implementation and laboratory tests of a winner takes all (WTA) artificial neural network (NN) on two microcontrollers (μC) with the ARM Cortex M3 and the AVR cores. The prospective application of this device is in wireless body sensor network (WBSN) in an on-line analysis of electrocardiograph (ECG) and electromyograph (EMG) biomedical signals. The proposed device will be used as a base station in the WBSN, acquiring and analysing the signals from the sensors placed on the human body. The proposed system is equiped with an analog-todigital converter (ADC), and allows for multi-channel acquisition of analog signals, preprocessing (filtering) and further analysis

Analog, Continuous Time, Fully Parallel, Programmable Image Processor Based on Vector Gilbert Multiplier

A conception as well as a CMOS implementation of the analog, ultra low power and fully parallel image processor have been presented in this paper. Proposed circuit bases on the 2-D FIR filters realized using the Gilbert vector multiplier. Proposed filter enables realization of various lowpass and highpass 2-D FIR filter masks. Both the mask dimensions and values of the filter coefficients can be programmed using several dozen digital signals and several DC currents. Proposed image processor does not use the clock generator, what simplifies the overall circuit's structure and reduces the noise level. An example (6times6) image processor that enables filtering with a 3times3 mask has been implemented in CMOS 0.18 mum process. This circuit calculates 36 pixels in parallel every 1 mus, dissipating power about 20 muW. The image resolution can be easily enlarged by a parallel connection of many designed 6times6 cells

Ultra Low Power Switched Current Finite Impulse Response Filter Banks Realized in CMOS 0.18 um technology

Ultra low power circuits are in high demand in many applications especially in wireless sensor networks (WSN), where energy is scavenged from environment. WSN systems contain different blocks, such as: sensors, filters, analog-to-digital converters, very often a simple processor and the RF front end block. This paper concerns ultra low power finite impulse response (FIR) filters and filter banks implemented in a switched current (SI) technique. In this paper new SI FIR filter structures and filter banks have been proposed. These circuits operate in the current mode and do not use operational amplifiers, what enables very low power dissipation on the level of several μW. Proposed filters incorporate transistors working under threshold level for the voltage supply that is in the range 0.5 – 0.7 V. The simulated attenuation in the stopband of the frequency response is limited to about 45 dB, what is due to different nonidealities, but such value is usually sufficient in WSN applications. The SI technique features many interesting mechanisms that simplify realization of analog filter banks. The signal samples that are stored in the delay lane are in SI filters copied to the filter coefficients using current mirrors. As a result, there exists the possibility to connect many sets of filter coefficients to a single delay line without the speed limitation. Ultra low power operation of proposed filters is also possible due to a special structure of the clock generator that only consists from switches and NOT gates

New Fast Training Algorithm Suitable For Hardware Kohonen Neural Networks Designed For Analysis Of Biomedical Signals

A new optimized algorithm for the learning process suitable for hardware implemented Winner Takes Most Kohonen Neural Network (KNN) has been proposed in the paper. In networks of this type a neighborhood mechanism is used to improve the convergence properties of the network by decreasing the quantization error. The proposed technique bases on the observation that the quantization error does not decrease monotonically during the learning process but there are some 'activity' phases, in which this error decreases very fast and then the 'stagnation' phases, in which the error does not decrease. The stagnation phases usually are much longer than the activity phases, which in practice means that the network makes a progress in training only in short periods of the learning process. The proposed technique using a set of linear and nonlinear filters detects the activity phases and controls the neighborhood R in such a way to shorten the stagnation phases. As a result, the learning process may be 16 times faster than in the classic approach, in which the radius R decreases linearly. The intended application of the proposed solution will be in Wireless Body Sensor Networks (WBSN) in classification and analysis of the EMG and the ECG biomedical signals

Hardware Implementation Issues of the Neighborhood Mechanism in Kohonen Self Organized Feature Maps

In this paper, we discuss an important problem of the selection of the neighborhood radius in the learning schemes of the Winner Takes Most Kohonen neural network. The optimization of this parameter is essential in case of hardware realization of the network given that the lower values of the radius can result in significant reduction of both the power dissipation and the chip area, even by 40-60% that is important in application of such networks in low power devices. The simulation studies reveal that using large initial values of the neighborhood radius usually is not the most optimal. For a wide range of the training parameters some optimal values, usually small, of the neighborhood radius may be indicated that allow for the minimization of the quantization error