A CMOS Monolithic Implementation of a Nonliniear Interconnection Module for a Corticonic Network

A nonlinear interconnection module for a corticonic network is designed and fabricated in a 0.6µm CMOS process. The module uses NMOS transistors in weak-inversion for nonlinearity. A calibration scheme is developed to compensate for the process and temperature variations of the circuit. The designed module has an area of 0.35 sq. mm2. It consumes 200mW of power, with 5V power supply. Simulation results show that the circuit is able to implement the target parametric coupling function accurately

A CMOS Monolithic Implementation of a Nonlinear Element for Arbitrary 1-D Map Generation

In a macroscopic approach, a single-chip cortical patch is designed based on a the model of a bifurcating neuron. In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic element is able to generate an arbitrary one-dimensional map with 12-bit resolution. The CMOS design employs a calibration scheme to maintain robustness against process variations. The element is fabrication in a 0.6um CMOS process, and it driven under signals with 1MHz frequency. It covers a die of 0.2 square mm, and consumes 40mW power, with a 5V supply

GBOPCAD: A Synthesis Tool for High-Performance Gain-Boosted Opamp Design

A systematic design methodology for high-performance gain-boosted opamps (GBOs) is presented. The methodology allows the optimization of the GBO in terms of ac response and settling performance and is incorporated into an automatic computer-aided design (CAD) tool, called GBOPCAD. Analytic equations and heuristics are first used by GBOPCAD to obtain a sizing solution close to the global optimum. Then, simulated annealings are used by GBOPCAD to find the global optimum. A sample opamp is designed by this tool in a 0.6-μm CMOS process. It achieves a dc gain of 80 dB, a unity-gain bandwidth of 836 MHz with 60o phase margin and a 0.0244% settling time of 5 ns. The sample/hold front-end of a 12-bit 50-MSample/s analog–digital converter was implemented with this opamp. It achieves a signal-to-noise ratio of 81.9 dB for a 8.1-MHz input signal

Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter

A new all-digital background calibration method, using a piecewise linear model to estimate the stage error pattern, is presented. The method corrects both linear and nonlinear errors. The proposed procedure converges in a few milliseconds and requires low hardware overhead, without the need of a high-capacity ROM or RAM. The calibration procedure is tested on a 0.6- µm CMOS pipeline analog-to-digital converter (ADC), which suffers from a high degree of nonlinear errors. The calibration gives improvements of 17 and 26 dB for signal-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, for the Nyquist input signal at the sampling rate of 33 MSample/s. The calibrated ADC achieves SNDR of 70.3 dB and SFDR of 81.3 dB at 33 MSample/s, which results in a resolution of about 12 b

Analytical and Experimental Studies of Thermal Noise in MOSFET\u27s

An analysis of the channel thermal noise in MOSFET\u27s, based on the one-dimensional charge sheet model, is presented. The analytical expression is valid in the strong, moderate, and weak inversion regions. The body effect on the device parameters relevant to the thermal noise is discussed. A measurement technique as well as experimental results of P- and N-MOSFET\u27s of a 1.2 µm radiation hard CMOS process are presented. The calculated channel thermal noise coefficient gamma as in id2/Δf=4kT γ gdo agrees well with experimental data for effective device channel length as short as 1.7µm

Cort-X II: Low Power Element Design of a Large-Scale Spatio-Temporaral Pattern Clustering System

Complex spatio-temporal patterns can be clustered using a network of parametrically coupled logistic maps. This paper describes the processing element design of such a Cort-X system. Each Cort-X element consists of a non-linear coupling (LC) and a non-linear dynamic element (IRON). The circuits are designed for low-power operation and to be robust against process variations. This has been accomplished by using openloop circuits, and a self-calibration technique that compensate for process variations. The circuits were implemented in a 0.25 um, 2.5V CMOS process and consumes a total of 12mW of power at 1MHz which is about a factor of 20 less power than previous realizations. This opens the possibility for building a large-scale Cort-X system on a chip for the recognition of complex spatio-temporal patterns

Transparant afwegen; Waarden en risico's beoordelen van voedselkwaliteit

Transparante beleidsafwegingen en bredere risicobeoordelingen lijken cruciaal voor het waarmaken van de maatschappelijke aspiraties die het ministerie van LNV zich op het gebied van voedselkwaliteit heeft gesteld. De implementatie van instrumenten die dergelijke afwegingen ondersteunen blijkt echter problematisch. In dit rapport wordt ingegaan op de toepassing van een TRansparant Afwegingskader (TRAK) en het instrument van een Brede Risicobeoordeling (BRB). Deze instrumenten bieden zeker kansen, maar een succesvolle implementatie zal tijd en energie vergen gezien de knelpunten die er tegenover staan. Transparent policy decisions and broader risk assessments seem to be crucial for fulfilling the social aspirations established by the Ministry of Agriculture, Nature and Food Quality with regard to food quality. However, the use of instruments which support such decision(making seems to be encountering problems. This report discusses the application of a Transparent Consideration Framework (TRansparant AfwegingsKader, TRAK) and a Broad Risk Assessment (Brede Risicobeoordeling, BRB). These instruments certainly offer potential, but successful implementation will take time and energy in view of the problems facing them

Noise Spectral Density Measurements of a Radiation Hardened CMOS Process in the Weak and Moderate Inversion

We have measured the noise of MOS transistors of the United Technology Microelectronics Center (UTMC) 1.2 µm radiation hardened CMOS P-well process from the weak to moderate inversion region. The noise power spectral densities of both NMOS and PMOS devices were measured from 1 KHz to 50 MHz. The bandwidth was chosen such that the important components of the spectral densities such as the white thermal noise and the l/f noise could be easily resolved and analyzed in detail. The effects of different device terminal DC biases and channel geometries on the noise are described

A CMOS Time to Digital Converter IC with 2 Level Analog CAM

A time to charge converter IC with an analog memory unit (TCCAMU) has been designed and fabricated in HP\u27s CMOS 1.2-µm n-well process. The TCCAMU is an event driven system designed for front end data acquisition in high energy physics experiments. The chip includes a time to charge converter, analog Level 1 and Level 2 associative memories for input pipelining and data filtering, and an A/D converter. The intervals measured and digitized range from 8-24 ns. Testing of the fabricated chip resulted in an LSB width of 107 ps, a typical differential nonlinearity of \u3c 35 ps, and a typical integral nonlinearity of \u3c 200 ps. The average power dissipation is 8.28 mW per channel. By counting the reference clock, a time resolution of 107 ps over ~ 1 s range could be realized