Temperature and Size Effect on the Electrical Properties of Monolayer Graphene based Interconnects for Next Generation MQCA based Nanoelectronics

Graphene interconnects have been projected to out-perform Copper interconnects in the next generation Magnetic Quantum-dot Cellular Automata (MQCA) based nano-electronic applications. In this paper a simple two-step lithography process for patterning CVD monolayer graphene on SiO2/Si substrate has been used that resulted in the current density of one order higher magnitude as compared to the state-of-the-art graphene-based interconnects. Electrical performances of the fabricated graphene interconnects were evaluated, and the impact of temperature and size on the current density and reliability was investigated. The maximum current density of 1.18 x 108 A/cm2 was observed for 0.3 μm graphene interconnect on SiO2/Si substrate, which is about two orders and one order higher than that of conventionally used copper interconnects and CVD grown graphene respectively, thus demonstrating huge potential in outperforming copper wires for on-chip clocking. The drop in current at 473 K as compared to room temperature was found to be nearly 30%, indicating a positive temperature coefficient of resistivity (TCR). TCR for all cases were studied and it was found that with decrease in width, the sensitivity of temperature also reduces. The effect of resistivity on the breakdown current density was analysed on the experimental data using Matlab and found to follow the power-law equations. The breakdown current density was found to have a reciprocal relationship to graphene interconnect resistivity suggesting Joule heating as the likely mechanism of breakdown

Area efficient in-plane nanomagnetic multiplier and convolution architecture design

In this study, we propose a nanomagnetic logic (NML) based 2 bit multiplier architecture design for the first time to the best of author's knowledge. This complex combinational logic (nanomagnetic multiplier) design proposed is built by exploiting shape, positional hybrid anisotropy and the ferromagnetically coupled fixed input majority gate. Subsequently, we extend this proposed multiplier architecture along with the NML adder architecture in introducing NML based convolution architecture design which is efficient in terms of number of nanomagnets, majority gates and clock-cycles. The proposed NML design yields 1/421%-72%, 1/426%-42%, 1/436%-63%, and 1/420%-68%, reduction in the required number of nanomagnets, majority gate, clock cycles and energy compared to the state-of-the-art designs. © 2021 The Author(s). Published by IOP Publishing Ltd

Effects of Orientation and Temperature on the Tensile Strength of Pristine and Defective Bi-Layer Graphene Sheet – A Molecular Dynamics Study

Molecular dynamics simulations with adaptive intermolecular reactive empirical bond order (AIREBO) potential were carried out to study the effect of temperature and orientation on the tensile strength of pristine and defective bilayer graphene (BLG) sheet. Results obtained reveal that the fall in tensile strength of pristine AA stacked BLG due to the presence of vacancy is significant at room temperature (300 K) but decreases at higher temperature (1073 K). Interestingly, this phenomenon reverses in case of AB stacked BLG, wherein the percentage fall in strength at higher temperature due to defect is more than that at room temperature. In order to understand these discrepancies in the results obtained, three case studies were conducted, and the results obtained suggested that when defects are present in armchair direction, this phenomenon occurs. The study also reveals that in case of AB stacked BLG, zigzag direction is more defect tolerant at room and high temperatures. Interestingly, variation of tensile strength due to the orientation is in good agreement with projections from potential energy concepts and theoretical calculations. We envisage that the study will provide useful information to the device engineers for the optimisation of the mechanical properties and convenient structural adaptation of bilayer graphene while working at wide range of temperatures

A novel and reliable interlayer exchange coupled nanomagnetic universal logic gate design

In this paper, we propose an interlayer exchange coupling (IEC) based 3D universal NAND/NOR gate design methodology for the reliable and robust implementation of nanomagnetic logic design as compared to the state-of-the art architectures. Owing to stronger coupling scheme as compared to the conventional dipole coupling, the random flip of the states of the nanomagnets (i.e. the soft error) is reduced resulting in greater scalability and better data retention at the deep sub-micron level. Results obtained from Object Oriented Micromagnetic Framework micromagnetic simulation show even at a Curie temperature of the nanomagnets coupled through IEC, the logic function works properly as opposed to dipole coupled nanomagnets which fails at 5 K when scaled down to sub 50 nm. Contemplating the fabrication challenges, the robustness of the IEC design was studied for structural defects, positional misalignment, shape, and size variations. This proposed 3D universal gate design methodology benefits from the miniaturization of nanomagnets as well as reduces the effect of thermally induced errors resulting in opening up a new perspective for nanomagnet based design in magneto-logic devices

Interlayer Exchange Coupled Based Nanomagnetic Multiplier Architecture Design Methodology

In this manuscript, Inter-Layer Exchange Coupled (IEC) based 2-bit multiplier architecture model methodology has been proposed here and to the best of author's knowledge is the first of its kind. Subsequently, the proposed model methodology has been executed using the extensively recognized Object Oriented Micro-Magnetic Framework (OOMMF) platform. The reliability of the IEC based multiplier model was determined by analyzing the temperature variation impact up to the Curie temperature. It was noticed that unlike the dipole coupled architecture, the IEC based multiplier model has the capability of operating even up to Curie temperature at sub-50nm justifying stability with respect to the temperature variations. © 2002-2012 IEEE

Interlayer exchange couple based reliable and robust 3-input adder design methodology

In this paper, a novel inter-layer exchange coupled (IEC) based 3-input full adder design methodology is proposed and subsequently the architecture has been implemented on the widely accepted micromagnetic OOMMF platform. The impact of temperature on the IEC coupled full-adder design has been analyzed up to Curie temperature. It was observed that even up to Curie temperature the IEC based adder design was able to operate at sub-50 nm as contrast to dipole coupled adder design which failed at 5 K for sub 50 nm. Simulation results obtained from OOMMF micromagnetic simulator shows, the IEC based adder design was at a lower energy state as compared to the dipole coupled adder indicating a more stable system and as the temperature of the design was increased, the total energy increased resulting in reduced stability. Potential explanation for the thermodynamic stability of IEC model lies in its energetically favored architecture, such that the total energy was lower than its dipole coupled counterparts. IEC architecture demonstrates supremacy in reliability and strength enabling NML to march towards beyond CMOS devices

Tunable intrinsic magnetic phase transition in pristine single-layer graphene nanoribbons

In this paper, we report on the interesting phenomenon of magnetic phase transitions (MPTs) observed under the combined influence of an electric field (E) and temperature (T) leading to a thermo-electromagnetic effect on the pristine single-layer zigzag graphene nanoribbon (szGNR). Density functional theory-based first principles calculations have been deployed for this study on the intrinsic magnetic properties of graphene. Interestingly, by tuning electric field (E) and temperature (T), three distinct magnetic phase behaviors, para-, ferro- and antiferromagnetic are exhibited in pristine szGNR. We have investigated the unrivaled positional parameters of these MPTs. MPT occurring in the system also follows a positional trend and the change in these positional parameters with regard to the size of the szGNR along with the varied E and T is studied. We propose a bow-tie schematic to induce the intrinsic magnetism in graphene and present the envisaged model of the processor application with the reported intrinsic MPT in szGNR. This fundamental insight into the intrinsic MPTs in graphene is an essential step towards developing graphene-based spin-transfer torque magnetoresistive random access memory, quantum computing devices, magnonics and spintronic memory application

Area-elficient interlayer signal propagation in 3D IC by introducing electron spin

Through Silicon Via (TSV) is the major technology in order to transmit data among various devices in 3D IC. Therefore higher concentration of TSV is required for higher packing density in 3D IC. In order to obtain high density of TSV, the dimensions of TSV needs to be reduced. This may be achieved by increasing the surface area per layer which will benefit in packing of more components for any operation including logic implementation. In this paper we introduce electron spin rather than charge for the first time for interlayer signal transmission in 3D IC resulting in area efficiency. Ansys electromagnetic simulator (Maxwell 2D and 3D) and OOMMF simulation supported by theoretical analysis specifies an average of 90% area reduction per layer of 3D IC as compared to state-of-the art TSV

Temperature and Size Effect on the Electrical Properties of Monolayer Graphene based Interconnects for Next Generation MQCA based Nanoelectronics

Graphene interconnects have been projected to out-perform Copper interconnects in the next generation Magnetic Quantum-dot Cellular Automata (MQCA) based nano-electronic applications. In this paper a simple two-step lithography process for patterning CVD monolayer graphene on SiO2/Si substrate has been used that resulted in the current density of one order higher magnitude as compared to the state-of-the-art graphene-based interconnects. Electrical performances of the fabricated graphene interconnects were evaluated, and the impact of temperature and size on the current density and reliability was investigated. The maximum current density of 1.18 ×108 A/cm2 was observed for 0.3 μm graphene interconnect on SiO2/Si substrate, which is about two orders and one order higher than that of conventionally used copper interconnects and CVD grown graphene respectively, thus demonstrating huge potential in outperforming copper wires for on-chip clocking. The drop in current at 473 K as compared to room temperature was found to be nearly 30%, indicating a positive temperature coefficient of resistivity (TCR). TCR for all cases were studied and it was found that with decrease in width, the sensitivity of temperature also reduces. The effect of resistivity on the breakdown current density was analysed on the experimental data using Matlab and found to follow the power-law equations. The breakdown current density was found to have a reciprocal relationship to graphene interconnect resistivity suggesting Joule heating as the likely mechanism of breakdown

Self-healing phenomena of graphene: potential and applications

The present study investigates the self healing behavior of both pristine and defected single layer graphene using a molecular dynamic simulation. Single layer graphene containing various defects such as preexisting vacancies and differently oriented pre-existing cracks were subjected to uniaxial tensile loading till fracture occurred. Once the load was relaxed, the graphene was found to undergo self healing. It was observed that this self healing behaviour of cracks holds irrespective of the nature of pre-existing defects in the graphene sheet. Cracks of any length were found to heal provided the critical crack opening distance lies within 0.3-0.5 nm for a pristine sheet and also for a sheet with pre-existing defects. Detailed bond length analysis of the graphene sheet was done to understand the mechanism of self healing of graphene. The paper also discusses the immense potential of the self healing phenomena of graphene in the field of graphene based sub-nano sensors for crack sensing