Japanese Encephalitis Virus Induce Immuno-Competency in Neural Stem/Progenitor Cells

BACKGROUND: The low immunogenicity of neural stem/progenitor cells (NSPCs) coupled with negligible expression of MHC antigens has popularized their use in transplantation medicine. However, in an inflammatory environment, the NSPCs express costimulatory molecules and MHC antigens, and also exhibit certain immunomodulatory functions. Since NSPCs are the cellular targets in a number of virus infections both during postnatal and adult stages, we wanted to investigate the immunological properties of these stem cells in response to viral pathogen. METHODOLOGY/PRINCIPAL FINDINGS: We utilized both in vivo mouse model and in vitro neurosphere model of Japanese encephalitis virus (JEV) infection for the study. The NSPCs residing in the subventricular zone of the infected brains showed prominent expression of MHC-I and costimulatory molecules CD40, CD80, and CD86. Using Flow cytometry and fluorescence microscopy, we observed increased surface expression of co-stimulatory molecule and MHC class I antigen in NSPCs upon progressive JEV infection in vitro. Moreover, significant production of pro-inflammatory cyto/chemokines was detected in JEV infected NSPCs by Cytokine Bead Array analysis. Interestingly, NSPCs were capable of providing functional costimulation to allogenic T cells and JEV infection resulted in increased proliferation of allogenic T cells, as detected by Mixed Lymphocyte reaction and CFSE experiments. We also report IL-2 production by NSPCs upon JEV infection, which possibly provides mitogenic signals to T cells and trigger their proliferation. CONCLUSION/SIGNIFICANCE: The in vivo and in vitro findings clearly indicate the development of immunogenicity in NSPCs following progressive JEV infection, in our case, JEV infection. Following a neurotropic virus infection, NSPCs possibly behave as immunogenic cells and contribute to both the innate and adaptive immune axes. The newly discovered immunological properties of NSPCs may have implications in assigning a new role of these cells as non-professional antigen presenting cells in the central nervous system

Post Quantum ECC on FPGA Platform

Post-quantum cryptography has gathered significant attention in recent times due to the NIST call for standardization of quantum resistant public key algorithms. In that context, supersingular isogeny based key exchange algorithm (SIKE) has emerged as a potential candidate to replace traditional public key algorithms like RSA and ECC. SIKE provides $\mathbf{O(\sqrt[4]{p})}$ classical security and $\mathbf{O(\sqrt[6]{p})}$ quantum security where $p$ is the characteristic of the underlying field. Additionally, SIKE has the smallest key sizes among all the post-quantum public algorithm, making it very suitable for bandwidth constrained environment. In this paper, we present an efficient implementation of SIKE protocol for FPGA based applications. The proposed architecture provides the same latency as that of the best existing implementation of SIKE protocol while consuming $48\%$ less DSPs and $58\%$ less block RAM resources. Thus, our design is substantially more efficient compared to that of existing implementations of SIKE

Exploiting the Order of Multiplier Operands: A Low Cost Approach for HCCA Resistance

Horizontal collision correlation analysis (HCCA) imposes a serious threat to simple power analysis resistant elliptic curve cryptosystems involving unified algorithms, for e.g. Edward curve unified formula. This attack can be mounted even in presence of differential power analysis resistant randomization schemes. In this paper we have designed an effective countermeasure for HCCA protection, where the dependency of side-channel leakage from a school-book multiplication with the underling multiplier operands is investigated. We have shown how changing the sequence in which the operands are passed to the multiplication algorithm introduces dissimilarity in the information leakage. This disparity has been utilized in constructing a zero-cost countermeasure against HCCA. This countermeasure integrated with an effective randomization method has been shown to successfully thwart HCCA. Additionally we provide experimental validation for our proposed countermeasure technique on a SASEBO platform. To the best of our knowledge, this is the first time that asymmetry in information leakage has been utilized in designing a side channel countermeasure

ECC on Your Fingertips: A Single Instruction Approach for Lightweight ECC Design in GF (p)

Lightweight implementation of Elliptic Curve Cryptography on FPGA has been a popular research topic due to the boom of ubiquitous computing. In this paper we propose a novel single instruction based ultra-light ECC crypto-processor coupled with dedicated hard-IPs of the FPGAs. We show that by using the proposed single instruction framework and using the available block RAMs and DSPs of FPGAs, we can design an ECC crypto-processor for NIST curve P-256, requiring only 81 and 72 logic slices on Virtes-5 and Spartan-6 devices respectively.To the best of our knowledge, this is the first implementation of ECC which requires less than 100 slices on any FPGA device family

Using Tweaks To Design Fault Resistant Ciphers

Side channel analysis and active fault analysis are now major threats to even mathematically robust cryptographic algorithms that are otherwise resistant to classical cryptanalysis. It is necessary to design suitable countermeasures to protect cryptographic primitives against such attacks. This paper focuses on designing encryption schemes that are innately secure against fault analysis. The paper formally proves that one such design strategy, namely the use of key-dependent SBoxes, is only partially secure against DFA. The paper then examines the fault tolerance of encryption schemes that use a key-independent secret tweak value for randomization. In particular, the paper focuses on a linear tweak based and a non-linear tweak based version of a recently proposed block cipher DRECON. The paper demonstrates that while both versions are secure against classical DFA, the non-linear tweak based version provides greater fault coverage against stronger fault models. This fact, together with the DPA resistance provided by the use of variable S-Boxes, makes DRECON a strong candidate for the design of secure cryptographic primitives. All claims have been validated by experimental results on a SASEBO GII platform

Side-Channel Watchdog: Run-Time Evaluation of Side-Channel Vulnerability in FPGA-Based Crypto-systems

Besides security against classical cryptanalysis, its important for cryptographic implementations to have sufficient robustness against side-channel attacks. Many countermeasures have been proposed to thwart side channel attacks, especially power trace measurement based side channel attacks. Additionally, researchers have proposed several evaluation metrics to evaluate side channel security of crypto-system. However, evaluation of any crypto-system is done during the testing phase and is not part of the actual hardware. In our approach, we propose to implement such evaluation metrics on-chip for run-time side channel vulnerability estimation of a cryptosystem. The objective is to create a watchdog on the hardware which will monitor the side channel leakage of the device, and will alert the user if that leakage crosses a pre-determined threshold, beyond which the system might be considered vulnerable. Once such alert signal is activated, proactive countermeasures can be activated either at the device level or at the protocol level, to prevent the impending side channel attack. A FPGA based prototype designed by us show low hardware overhead, and is an effective option that avoids the use of bulky and inconvenient on-field measurement setup