81 research outputs found

    ERASER: Towards Adaptive Leakage Suppression for Fault-Tolerant Quantum Computing

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    Quantum error correction (QEC) codes can tolerate hardware errors by encoding fault-tolerant logical qubits using redundant physical qubits and detecting errors using parity checks. Leakage errors occur in quantum systems when a qubit leaves its computational basis and enters higher energy states. These errors severely limit the performance of QEC due to two reasons. First, they lead to erroneous parity checks that obfuscate the accurate detection of errors. Second, the leakage spreads to other qubits and creates a pathway for more errors over time. Prior works tolerate leakage errors by using leakage reduction circuits (LRCs) that modify the parity check circuitry of QEC codes. Unfortunately, naively using LRCs always throughout a program is sub-optimal because LRCs incur additional two-qubit operations that (1) facilitate leakage transport, and (2) serve as new sources of errors. Ideally, LRCs should only be used if leakage occurs, so that errors from both leakage as well as additional LRC operations are simultaneously minimized. However, identifying leakage errors in real-time is challenging. To enable the robust and efficient usage of LRCs, we propose ERASER that speculates the subset of qubits that may have leaked and only uses LRCs for those qubits. Our studies show that the majority of leakage errors typically impact the parity checks. We leverage this insight to identify the leaked qubits by analyzing the patterns in the failed parity checks. We propose ERASER+M that enhances ERASER by detecting leakage more accurately using qubit measurement protocols that can classify qubits into ∣0⟩,∣1⟩|0\rangle, |1\rangle and ∣L⟩|L\rangle states. ERASER and ERASER+M improve the logical error rate by up to 4.3×4.3\times and 23×23\times respectively compared to always using LRC.Comment: Will appear in the International Symposium on Microarchitecture (MICRO) 2023 in Octobe

    Driven transport of active particles through arrays of symmetric obstacles

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    We numerically examine the driven transport of an overdamped self-propelled particle through a two-dimensional array of circular obstacles. A detailed analysis of transport quantifiers (mobility and diffusivity) has been performed for two types of channels, {\it channel I} and {\it channel II}, that respectively correspond to the parallel and diagonal drives with respect to the array axis. Our simulation results show that the signatures of pinning actions and depinning processes in the array of obstacles are manifested through excess diffusion peaks or sudden drops in diffusivity, and abrupt jumps in mobility with varying amplitude of the drive. The underlying depinning mechanisms and the associated threshold driving strength largely depend on the persistent length of self-propulsion. For low driving strength, both diffusivity and mobility are noticeably suppressed by the array of obstacles, irrespective of the self-propulsion parameters and direction of the drive. When self-propulsion length is larger than a channel compartment size, transport quantifiers are insensitive to the rotational relaxation time. Transport with diagonal drives features self-propulsion-dependent negative differential mobility. The amplitude of the negative differential mobility of an active particle is much larger than that of a passive one. The present analysis aims at understanding the driven transport of active species like, bacteria, virus, Janus Particle etc. in porous medium.Comment: Accepted for publication in JCP (October 2023

    A Formal Treatment of Deterministic Wallets

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    In cryptocurrencies such as Bitcoin or Ethereum, users control funds via secret keys. To transfer funds from one user to another, the owner of the money signs a new transaction that transfers the funds to the new recipient. This makes secret keys a highly attractive target for attacks and has led to prominent examples where millions of dollars worth in cryptocurrency were stolen. To protect against these attacks, a widely used approach are so-called hot/cold wallets. In a hot/cold wallet system, the hot wallet is permanently connected to the network, while the cold wallet stores the secret key and is kept without network connection. In this work, we propose the first comprehensive security model for hot/cold wallets and develop wallet schemes that are provably secure within these models. At the technical level, our main contribution is to provide a new, provably secure ECDSA-based hot/cold wallet scheme that can be integrated into legacy cryptocurrencies such as Bitcoin. Our scheme makes several subtle changes to the BIP32 proposal and requires a technically involved security analysis

    Atmospheric Cold Plasma: A Brief Journey and Therapeutic Applications from Wound Healing to Cancer Biology

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    Cold Atmospheric Plasma (CAP) has now become a well-known new edge technology in the field of biomedical science to agriculture and food technology. Ionized gas known as cold atmospheric plasma has recently been the subject of intense inquiry by scientists for its potential application for treatment in oncology and dentistry. Air, Helium, Argon, Nitrogen, and other gases can all be used to create Cold Atmospheric Plasma. Cold plasma can effectively and safely inactivate spores, bacteria, fungi, viruses, and small molecules and thereby improving wound healing, combating microbial infections, and treating skin conditions with great efficiency. Interestingly the in vitro and in vivo demonstration of CAP has shown promising applications in cancer healing and treatment. The most widely employed technique for producing and sustaining a low-temperature plasma for use in technological and scientific applications involves applying an electric field to a neutral gas. The non-equilibrium atmospheric pressure plasma jet (NAPPJ) and the dielectric barrier discharge (DBD) have both been widely used in biomedical applications. This review aims to evaluate the emerging plasma technology - the basic science, technical aspects and provide insights of biomedical application in diverse area

    Exploiting the Order of Multiplier Operands: A Low Cost Approach for HCCA Resistance

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    Horizontal collision correlation analysis (HCCA) imposes a serious threat to simple power analysis resistant elliptic curve cryptosystems involving unified algorithms, for e.g. Edward curve unified formula. This attack can be mounted even in presence of differential power analysis resistant randomization schemes. In this paper we have designed an effective countermeasure for HCCA protection, where the dependency of side-channel leakage from a school-book multiplication with the underling multiplier operands is investigated. We have shown how changing the sequence in which the operands are passed to the multiplication algorithm introduces dissimilarity in the information leakage. This disparity has been utilized in constructing a zero-cost countermeasure against HCCA. This countermeasure integrated with an effective randomization method has been shown to successfully thwart HCCA. Additionally we provide experimental validation for our proposed countermeasure technique on a SASEBO platform. To the best of our knowledge, this is the first time that asymmetry in information leakage has been utilized in designing a side channel countermeasure

    ECC on Your Fingertips: A Single Instruction Approach for Lightweight ECC Design in GF (p)

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    Lightweight implementation of Elliptic Curve Cryptography on FPGA has been a popular research topic due to the boom of ubiquitous computing. In this paper we propose a novel single instruction based ultra-light ECC crypto-processor coupled with dedicated hard-IPs of the FPGAs. We show that by using the proposed single instruction framework and using the available block RAMs and DSPs of FPGAs, we can design an ECC crypto-processor for NIST curve P-256, requiring only 81 and 72 logic slices on Virtes-5 and Spartan-6 devices respectively.To the best of our knowledge, this is the first implementation of ECC which requires less than 100 slices on any FPGA device family
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