A Temporal Logic Based Theory of Test Coverage and Generation

This paper presents a theory of test coverage and generation from specifications written in extended finite state machines (EFSMs). We investigate a family of coverage criteria based on the information of control flow and data flow in EFSMs and characterize them using the temporal logic CTL. We discuss the complexity of minimal cost test generation and describe a simple heuristic which uses the capability of model checkers to construct counterexamples. Our approach extends the range of applications of model checking from automatic verification of finite state systems to automatic test generation from finite state systems

Protocol-Inspired Hardware Testing

The relevance of protocol conformance testing techniques to hardware testing is discussed. It is shown that the ioconf (input-output conformance) approach used in protocol testing can be applied to generate tests for a synchronous hardware design using its formal specification. The generated tests are automatically applied to a circuit by a VHDL testbench, thus giving confidence that the hardware design meets its high-level formal specification. Case studies illustrate how the ideas can be applied to standard hardware verification benchmarks such as the Single Pulser and Black-Jack Dealer

Analysis of composition complexity and how to obtain smaller canonical graphs

We discuss an open problem in construction of Reduced Ordered Binary Decision Diagrams (ROBDDs) using composition, and prove that the worst case complexity of the construction is truly cubic. With this insight we show that the process of composition naturally leads to the construction of (even exponentially) compact partitioned-OBDDs (POBDDs) [12]. Our algorithm which incorporates dynamic partitioning, leads to the most general (and compact) form of POBDDs- graphs with multiple root variables. To show that our algorithm is robust and practical, we have analyzed some well known problems in Boolean function representation, verification and finite state machine analysis where our approach generates graphs which are even orders of magnitude smaller.

Automatic Abstraction for Verification of Timed Circuits and Systems

This paper presents a new approach for verication of asynchronous circuits by using automatic abstraction. It attacks the state explosion problem by avoiding the generation of a at state space for the whole design. Instead, it breaks the design into blocks and conducts veri cation on each of them. Using this approach, the speed of verication improves dramatically