Synthesis from specifications : basic concepts

The need has evolved for a synthesis tool at the computer system level. SpecSyn is one such tool. Basically, it will view the world as a set of chips communicating via protocols. Thus, an abstract specification would get synthesized into a set of one or more interconnected chips. From that point, detail is added to each chip's specification until its structure is synthesized or it is determined that a prefabricated chip similar in functionality can be used.Features of such a tool include executable specifications from which to synthesize, constraint driven partitioning of the specifications into components (chips) and synthesis of interfaces between them, translation into VHDL and synthesis into VHDL structures of micro-architectural components, and the use of other tools (e.g. MILO, a micro-architecture and logic optimizer, and LES, a layout expert system) to evaluate the quality of the chip layout generated from VHDL description.A major component of SpecSyn is SpecCharts, a high level specification language amenable to system level synthesis, able to represent designs from system to register transfer levels. The language consists of a hierarchy of states, represented in combined graphical and textual form, at the same time catering to the expression of concurrent behavior and specification of constraints. With it we have specified several Intel chips as well as higher level systems, and have found it to be quite powerful and easy to use.SpecSyn will have a graphical interface, from which the user can at any time view or edit a SpecChart, translate to VHDL and simulate, view statistics provided by estimators (such as area, speed, and pins), store and retrieve SpecCharts, apply basic Spec Chart operations, as well as apply the partitioning algorithms or interface synthesizer. Providing access to a wide range of tools, having a single language represent the design throughout the synthesis process, and having user specified constraints allow the user to have varying amounts of control over the synthesis process

Constant-time cost evaluation for behavioral partitioning

Given a system behavioral specification, partitioning can be used to distribute among chips the processes, procedures, and storage elements that comprise the specification. We introduce a technique for constant-time recomputation of pin, area, and execution-time estimates for a behavioral partitioning move. The technique permits fast, accurate estimations of a large number of partitionings, thus enabling better results than approaches which attain tractable computation time by using gross estimates or less thorough partitioning algorithms. The key to our technique is the isolation and extraction before partitioning of the basic design attributes needed for estimation, and the updating of this information in constant-time for each move. The estimation models are almost as detailed as those presented in previous estimation approaches not intended for constant-time update. The results we provide indicate the speed and practicality of our estimation approach in conjunction with sophisticated partitioning algorithms

Incorporating VHDL signal/wait semantics into synthesis

VHDL signals and wait statements provide great expressive power for behavioral descriptions. However, due to their simulation semantics, most high-level synthesis tools do not handle these constructs and severely restrict their use, eliminating much of their power. In this report, we introduce a set of transformations to convert signals and wait statements to equivalent constructs that are easily handled by high-level synthesis tools. They greatly enlarge the synthesizable VHDL subset, thus increasing the usefulness and practicality of the language as an input to high-level synthesis. These transformations can also serve as a basis for converting a VHDL process to a form suitable for generation of software

Semantics and synthesis of signals in behavioral VHDL

Signals are a fundamental part of VHDL behavioral descriptions. There are many kinds of VHDL signals, each possesing complex and hence often misunderstood semantics. The result is that synthesis tools often inadequately address synthesis of signals. In this report, we first make clear the semantics of the various signal kinds shared by multiple processes through the use of conceptual hardware, rather than just text. Second, with the semantics firmly understood, we discuss techniques and issues in synthesizing actual hardware for shared signals. This information can be used to take a step towards synthesizing correct hardware from VHDL descriptions while greatly reducing current restrictions imposed by synthesis tools on allowable VHDL behavior

Non-Orthogonal Multiple Access for FSO Backhauling

We consider a free space optical (FSO) backhauling system which consists of two base stations (BSs) and one central unit (CU). We propose to employ non-orthogonal multiple access (NOMA) for FSO backhauling where both BSs transmit at the same time and in the same frequency band to the same photodetector at the CU. We develop a dynamic NOMA scheme which determines the optimal decoding order as a function of the channel state information at the CU and the quality of service requirements of the BSs, such that the outage probabilities of both BSs are jointly minimized. Moreover, we analyze the performance of the proposed NOMA scheme in terms of the outage probability over Gamma-Gamma FSO turbulence channels. We further derive closed-form expressions for the outage probability for the high signal-to-noise ratio regime. Our simulation results confirm the analytical derivations and reveal that the proposed dynamic NOMA scheme significantly outperforms orthogonal transmission and existing NOMA schemes.Comment: This paper has been submitted to IEEE WCNC 201

Statistical Modeling of FSO Fronthaul Channel for Drone-based Networks

We consider a drone-based communication network, where several drones hover above an area and serve as mobile remote radio heads for a large number of mobile users. We assume that the drones employ free space optical (FSO) links for fronthauling of the users' data to a central unit. The main focus of this paper is to quantify the geometric loss of the FSO channel arising from random fluctuation of the position and orientation of the drones. In particular, we derive upper and lower bounds, corresponding approximate expressions, and a closed-form statistical model for the geometric loss. Simulation results validate our derivations and quantify the FSO channel quality as a function of the drone's instability, i.e., the variation of its position and orientation.Comment: This paper has been submitted to ICC 201

New Phase Transitions in Optimal States for Memory Channels

We investigate the question of optimal input ensembles for memory channels and construct a rather large class of Pauli channels with correlated noise which can be studied analytically with regard to the entanglement of their optimal input ensembles. In a more detailed study of a subclass of these channels, the complete phase diagram of the two-qubit channel, which shows three distinct phases is obtained. While increasing the correlation generally changes the optimal state from separable to maximally entangled states, this is done via an intermediate region where both separable and maximally entangled states are optimal. A more concrete model, based on random rotations of the error operators which mimic the behavior of this subclass of channels is also presented.Comment: 13 pages, Late

SpecCharts : a language for system level specification and synthesis

SpecCharts is a new language intended for system level specification and synthesis. SpecCharts represent a multi-module system with a hierarchy of state diagrams, catering to the expression of concurrent behavior, and using VHDL sequential statement semantics to describe a leaf state's (a state not composed of substates) functionality. The language permits protocol based data transfer, estimations, constraints, and state based description, all of which enable the omission of detail and thus enhance the comprehension of a system's behavior. The language is intended to represent a design throughout the system and chip levels of synthesis. i.e. converting an abstract specification into a set of one or more interconnected chips/modules, each having a well defined structure or being bound to a prefabricated component. Since good system design requires an executable specification language, SpecCharts can be simulated via automatic conversion to VHDL