Analyzing the linearity of ramp waveforms generated by means of AWG

Highly linear ramp waveforms are important in a variety of industrial processes, control systems, and test and measurement applications. The generation of ramp waveforms can be accomplished in several ways by means of both dedicated circuits and arbitrary waveform generators; the latter ones also grant the widest configurability of the output waveform both in terms of time and amplitude parameters. But, the waveforms generated by means of arbitrary waveform generators are characterized by piecewise time domain evolution. The underneath piecewise frame always implies a reduced conformity of the generated waveform to the intended one, even if the waveform is smoothed by means of a low-pass filter integrated in the generation chain. Conformity analyses can be carried out both in time and frequency domain, and their results expressed either by means of an error waveform or by pointing out the undesired spectral contributions. Typically, the insights allowed by the spectral analysis greatly help in both understanding the causes of poor conformity, and docum enting the precision of the output waveform. Hereinafter, first a general explanation of the mechanisms that originate the distortion contributions and reduce the conformity of a piecewise waveform to the intended one is given. Then, the attention is focused on ramp waveforms generated by means of arbitrary waveform generators and a thorough analysis of their conformity to an ideal ramp is carried out

Sampling and time–interleaving strategies to extend high speed digitizers bandwidth

Measuring signals in ultra-fast electronic systems requires high-end digital oscilloscopes characterized by extremely large analog bandwidths, up to 100 GHz, and digitization capabilities at least up to the corresponding Nyquist rate, i.e. 200 GS/s or above. This performance can be achieved by means of architectures that implement suitable methodologies, based on synchronous time interleaving, digital bandwidth interleaving, or hybrid approaches merging and exploiting both of the previous concepts. Each of these architectures typically includes a number of innovations, concerning both methods and hardware solutions, which are either covered by patents or classified. The paper presents the architecture of an original high-speed digitizer that exploits frequency conversion and time interleaving techniques. Thanks to the use of 4 time-interleaved channels, each one consisting of a state-of-the-art sampler and an ADC, the proposed solution can increase fourfold the analog bandwidth with respect to the individual ADCs, achieving noise reduction with respect to traditional time interleaved architectures

A wide-band DSO architecture based on three time interleaved channels

A DSO architecture consisting of three parallel channels, each of which includes a sampler and a cascaded synchronous ADC, is presented. Thanks to suitable time and frequency interleaving operations, the overall system bandwidth is three times that of each single ADC. The proposed architecture exploits in a better way the hardware resources with respect to classical time interleaving-based solutions, and grants lower noise floor with respect to pure frequency interleaving alternatives. It can approach the performance of the state of the art DSOs, namely 100 GHz analog bandwidth and 240 GSa/s sampling frequency, by exploiting three identical ADCs characterized by 33 GHz input bandwidth and 80 GSa/s sampling frequency