Decision-theoretic exploration of multiProcessor platforms

In this paper, we present an efficient technique to perform design space exploration of a multi-processor platform that minimizes the number of simulations needed to identify the power-performance approximate Pareto curve. Instead of using semi-random search algorithms (like simulated anneal-ing, tabu search, genetic algorithms, etc.), we use domain knowledge derived from the platform architecture to set-up exploration as a decision problem. Each action in the decision-theoretic framework corresponds to a change in the platform parameters. Simulation is performed only when information about the probability of action outcomes be-comes insufficient for a decision. The algorithm has been tested with two multi-media industrial applications, namely an MPEG4 encoder and an Ogg-Vorbis decoder. Results show that the exploration of the number of processors and two-level cache size and policy, can be performed with less than 15 simulations with 95 % accuracy, increasing the ex-ploration speed by one order of magnitude when compared to traditional operation research techniques. 1

Numb Expression Contributes to the Maintenance of an Undifferentiated State in Human Epidermis.

The epidermis is a stratified epithelium with a stem cell subpopulation in the basal layer that constantly replicates and periodically detaches from the base, undergoing a differentiation process that involves various developmental signals and regulatory pathways. During the last 10 years, a number of studies tried to elucidate the intricate scenario that maintains the epithelial shield during the entire life span. In our study, we investigated the role of Numb in the skin compartment and, in particular, its involvement in stem cell maintenance. Numb expression in the skin compartment was assessed by immunofluorescence and immunohistochemistry analysis. We evaluated Numb expression in primary epithelial cells at various differentiative stages. Moreover, we overexpressed Numb in the isolated population enriched for undifferentiated progenitors to establish its involvement in in vitro differentiation. We demonstrated that Numb in high-proliferating epithelial undifferentiated progenitors contributes to the maintenance of an undifferentiated state. This regulation involves the E3 ligases Itch binding. Moreover, the analysis of a cohort of cutaneous carcinomas showed that Numb is highly expressed in squamous cell carcinoma (SCC), where we observed a direct correlation between the expression of Numb and Ki-67. Our data indicate for the first time that Numb is involved in the maintenance of the undifferentiated proliferating stem cell pool in the epithelial basal layer and its expression could become a new marker in skin cancer

Influence of caching and encoding on power dissipation of system-level buses for embedded systems

his paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed model can consider any cache configuration in terms of size, associativity and block. It includes also the most widely adopted power oriented encoding techniques for data and address buses. Experimental results show how the proposed model can be effectively adopted to configure the memory hierarchy and the system bus architecture from the power point of view

Power estimation for architectural exploration of HW/SW communication on system-level buses

The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching activity of the on-chip and off-chip buses at the system-level has been defined to evaluate the power dissipation and to compare the effectiveness of power optimization techniques. The paper aims at providing a framework for architectural exploration of a system design, focusing on the power consumption estimation of memory communication. Experimental results, conducted on bus streams generated by a real microprocessor and a stream generator, show how the variation of cache parameters and the introduction of bus encoding at the different levels on the memory hierarchy can affect the system power dissipation. Therefore, the proposed model can be effectively adopted to appropriately configure the hierarchy and the system bus architecture from the power standpoint

Multi-Accuracy Power and Performance Transaction-Level Modeling

This paper introduces a modeling and simulation technique that extends transaction-level modeling (TLM) to support multi-accuracy models and power estimation. This approach provides different combinations of power and performance models, and the switching of model accuracy during simulation, allowing the designer to trade off between simulation accuracy and speed at runtime. This is particularly useful during the exploration phase of a design, when the designer changes the features or the parameters of the design, trying to satisfy its constraints. Usually, only limited portions of a system are affected by a single parameter change, and therefore, it is possible to fast-simulate uninteresting sections of the application. In particular, we show how to extend the TLM and modify the SystemC kernel to support multiaccuracy features. The proposed methodology has been tested on several benchmarks, among which is an MPEG4 encoder, showing that simulation speed can be increased of one order of magnitude.On the same benchmarks, we also show how it is possible to choose the optimal performance simulation accuracy for a given power model, maximizing simulation speed for the desired accuracy

Automatic Generation of Error Control Codes for Computer Applications

This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of Error Control Codes (ECCs) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous Single Error Correcting (SEC) - Double Error Detecting (DED) - Single Byte Error Detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DEDSBD codes with Odd-bit-per-byte Error Correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card. The proposed tool chooses the best suited error control code for the characteristics of the application and the design constraints and returns the VHDL description of the encoding/decoding circuits. The tool has been successfully applied for the design of a 64 data bit ECC contained in an ASIC designed for a multiprocessor system. Keywords--..

Power Exploration for Embedded VLIW Architectures

reserved4M. Sami; D. Sciuto; C. Silvano; V. ZaccariaSami, Mariagiovanna; Sciuto, Donatella; Silvano, Cristina; Zaccaria, Vittori