SITARe: a fast simulation tool for the analysis of disruptive effects on electronics

This paper is devoted to an exhaustive presentation of a fast computation numerical tool, dedicated to the simulation of transient currents induced by stochastic events in microelectronic devices. This is a part of a numerical platform, SITARe, combining a spice simulator with the semi-analytical model presented here. The paper describes the theoretical model, the calibration. An instance of application illustrates the ability of the tool

SITARe: a fast simulation tool for the analysis of disruptive effects on electronics

This paper is devoted to an exhaustive presentation of a fast computation numerical tool, dedicated to the simulation of transient currents induced by stochastic events in microelectronic devices. This is a part of a numerical platform, SITARe, combining a spice simulator with the semi-analytical model presented here. The paper describes the theoretical model, the calibration. An instance of application illustrates the ability of the tool

Low Power Radio Frequency Transceiver with Built-In-Tuning of the Local Oscillator for Open Loop Modulation

International audienc

Improvement of a VCO concept for low energy particule detection and recognition

International audienceA way of improvement of an oscillator concept, dedicated to detection and tracking of low energy particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a VCO response. In order to improve the correlation between the input current and the oscillator response, a new way of VCO implementation is proposed. The new output parameter variations are analyze

Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation

International audienceThis article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC B

TCAD investigation of zero-cost high voltage transistor architectures for logic memory circuits

International audienceIn this paper, a new device architecture has been studied by TCAD process simulations in order to provide the improvements on the electrical characteristics. We focus mainly on the drain-bulk junction breakdown voltage, of a double 130 nm poly gate transistor for Non-Volatile Memory technology. It is used as a word line select transistor, handling the drain voltage up to 13 V. The proposed structure has been implemented on silicon and the electrical measurements demonstrate the good predictability given by simulations. Finally, a new zero-cost added process asymmetric architecture is also studied to propose further improvements in terms of footprint or electrical characteristics

Multi-level control of resistive ram (Rram) using a write termination to achieve 4 bits/cell in high resistance state

RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell (MLC) RRAM operation without the need of any read verification. RRAM quad-level cell (QLC) capability with 4 bits/cell is demonstrated for the first time. QLC is implemented based on a strict control of the cell programming current of 1T-1R HfO2-based RRAM cells. From a design standpoint, a self-adaptive write termination circuit is proposed to control the RESET operation and provide an accurate tuning of the analog resistance value of each cell of a memory array. The different resistance levels are obtained by varying the compliance current in the RESET direction. Impact of variability on resistance margins is simulated and analyzed quantitatively at the circuit level to guarantee the robustness of the proposed MLC scheme. The minimal resistance margin reported between two consecutive states is 2.1 kΩ along with an average energy consumption and latency of 25 pJ/cell and 1.65 µs, respectively.Quantum & Computer EngineeringComputer Engineerin