FPGA partial reconfiguration in software Defined radio devices

Many SDR systems make effective use of FPGAs for data acquisition and heavy lifting DSP processing. This has resulted in several dedicated frameworks being developed, RFNoC being the most renowned. Even though FPGAs fabrics are, by their nature, reconfigurable, SDR systems often fail in exploiting this interesting opportunity at run-time. In this paper, we show how it is possible to make effective use of the Partial Reconfiguration capabilities of modern FPGA devices, extending the range of applications RFNoC can be applied to. In particular, it allows the live reconfiguration of signal processing chains, for instance to switch between wireless standards. This results in a better use of the limited FPGA resources by time-sharing them between processing blocks. Unfortunately, support for Partial Reconfiguration is not yet available in the software stack of commercially-available SDR devices. Our work thus aims at encouraging its integration

Transparent live code offloading on fpga

Even though it seems that FPGAs have finally made the transition from research labs to the consumer devices’ market, programming them remains challenging. Despite the improvements made by High-Level Synthesis (HLS), which removed the language and paradigm barriers that prevented many computer scientists from working with them, producing a new design typically requires at least several hours, making data- and context-dependent adaptations virtually impossible. In this paper we present a new framework that off-loads, onthe- fly and transparently to both the user and the developer, computationally-intensive code fragments to FPGAs. While the performance should not surpass that of hand-crafted HDL code, or even code produced by HLS, our results come with no additional development costs and do not require producing and deploying a new bit-stream to the FPGA each time a change is made. Moreover, since optimizations are made at run-time, they may fit particular datasets or usage scenarios, something which is rarely foreseeable at design or compile time. Our proposal revolves around an overlay architecture that is pre-programmed on the FPGA and dynamically reconfigured by our framework to execute code fragments extracted from the Data Flow Graph (DFG) of computational intensive routines. We validated our solution using standard benchmarks and proved we are able to off-load to FPGAs without developer’s intervention

Transparent FPGA flow

In this demo we propose an automated flow that allows the transparent execution of ordinary code on a heterogeneous platform including an FPGA. Our solution requires no change in the code, not even pragma indications to guide the optimization, and dynamically adapts its behaviour to the available data and the workload of the system. Thus, the developer does not need to be aware of the target platform details, nor she has to forecast usage patterns to prevent performance bottlenecks, as the system transparently identifies parallelizable, computationally-intensive code fragments and dispatches them to a data flow overlay architecture built on top of the FPGA. Since the bitstream we use is fixed, and contrary to HLS, we can alter the functionalities offered by the FPGA on-the-fly to adapt them to current usage. Finally, since we operate at the LLVM's Intermediate Representation (IR) level, our approach is language-agnostic