Design of a Configurable 4-Channel Analog Front-End for EEG Signal Acquisition on 180nm CMOS Process

In this work, a 4-channel Analog Front-End (AFE) circuit has been proposed for EEG signal recording. For EEG recording systems, the AFE may handle a wide range of sensor inputs with high input impedance, adjustable gain, low noise, and wide bandwidth. The buffer or current-to-voltage converter block (BCV), which can be set to operate as a buffer or a current-to-voltage converter circuit, is positioned between the electrode and the main amplifier stages of the AFE to achieve high input impedance and work with sensor signal types. A chopper capacitively-coupled instrumentation amplifier (CCIA) is positioned after the BCV as the main amplifier stage of the AFE to reduce input-referred noise and balance the impedance of the overall AFE system. A programmable gain amplifier (PGA) is the third stage of the AFE that allows the overall gain of the AFE to be adjusted. The suggested AFE operates in a wide frequency range of 0.5 Hz to 2 kHz with a high input impedance bigger than 2TΩ, and it is constructed and simulated using a 180nm CMOS process. With the lowest 100-dB CMRR and low input-referred noise of 1.8 µVrms, the AFE can achieve low noise efficiency. EEG signals can be acquired with this AFE system, which is very useful for detecting epilepsy and seizures

A FLEXIBLE HIGH-BANDWIDTH LOW-LATENCY MULTI-PORT MEMORY CONTROLLER

Multi-port memory controllers (MPMCs) have become increasingly important in many modern applications due to the tremendous growth in bandwidth requirement. Many approaches so far have focused on improving either the memory access latency or the bandwidth utilization for specific applications. Moreover, the application systems are likely to require certain adjustments to connect with an MPMC, since the MPMC interface is limited to a single-clock and single-data-width domain. In this paper, we propose efficient techniques to improve the flexibility, latency, and bandwidth of an MPMC. Firstly, MPMC interfaces employ a pair of dual-clock dualport FIFOs at each port, so any multi-clock multi-data-width application system can connect to an MPMC without requiring extra resources. Secondly, memory access latency is significantly reduced because parallel FIFOs temporarily keep the data transfer between the application system and memory. Lastly, a proposed arbitration scheme, namely window-based first-come-first-serve, considerably enhances the bandwidth utilization. Depending on the applications, MPMC can be properly configured by updating several internal configuration registers. The experimental results in an Altera Cyclone V FPGA prove that MPMC is fully operational at 150 MHz and supports up to 32 concurrent connections at various clocks and data widths. More significantly, achieved bandwidth utilization is approximately 93.2% of the theoretical bandwidth, and the access latency is minimized as compared to previous designs

Facile Synthesis of Carbon Quantum Dots by Plasma-liquid Interaction Method

Carbon quantum dots (CQDs) are a novel type of fluorescent nano-materials with various unique properties. They are recently attracting enormous interest due to their superiority in water solubility, chemical inertness, low toxicity, ease of functionalization as well as resistance to photo-bleaching and potential applications in biomedical indication, photo-catalysis, energy conversion, optoelectronics, and sensing. In this work, we present a facile and environmentally friendly synthesis of CQDs based on plasma - liquid interaction method. This is a single-step method and does not use toxic chemicals. The size distribution of obtained CQDs is rather uniform at approximately 3 nm. The emission peak of CQDs shifts from 427 nm to 523 nm as the excitation wavelength is varied from 340 nm to 460 nm. The non-equilibrium reactive chemistry of plasma liquid interaction is responsible for acceleration of the CQDs formation process

The Memorism Processor: Towards a Memory-Based Artificially Intelligence Complementing the von Neumann Architecture

Central processing unit (CPU) and graphics processing unit (GPU) are weak (“weak” means inefficiency) at detecting information represented by search, reference and recognition for reason of computer architecture. The memorism processor is a memory base processor which complements CPU's weak point. The two memorism processors called set operating processors (SOP) and database processors (DBP) are the device technology that covers the processing that CPUs and GPUs are not good at. Their profitability in various information processing including rapidity and energy saving performance has been proved and therefore there are great expectations for them as a device technology in the post-Moore era. In addition to the conventional SOPs and DBPs, we have developed cross operating processors (XOP), which are excellent at combination/comparison operation and therefore we have applied for a patent of it. These three memorism processors are expected to play a great role in the evolution of the artificial intelligence. This paper is contributed as continuation of [K. Inoue, M. Odaka and C.-K. Pham: Memorism Processor which complements weak point of von Neumann processor, Proc. SII2016, pp. 267-270, 2016], and the authors propose computation that is more suitable for the artificial intelligence era

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance