Drivers' Activities and Information Needs in an Automated Highway System

DTFH61-92-C-00100These experiments investigated what drivers do when traveling under automated control, and what information they would like to have available during that time. Eighteen drivers ages 25 through 34 and 18 drivers age 65 or older participated in the first two experiments; 6 drivers participated in the third experiment. All experiments were conducted in the Iowa Driving Simulator. The driver drove the simulator vehicle onto a freeway and then moved to the center lane; following a period of manual driving, control was transferred to the AHS, and the driver traveled under automated control for at least 34 min. In the first two experiments, which were run together and consisted of a single trial for each driver, driver activities were videotaped for later analysis. In addition, a laptop computer was mounted near the driver that offered several types of information. Drivers were given a questionnaire after the experiment to allow ratings of and comments on the various information types. In the third experiment, each driver participated in eight trials, once each in the morning and afternoon on 4 days, simulating a commuter experience. Driver activities were again videotaped for later analysis, but there was no laptop computer available. RESULTS: In the two noncommuter experiments, drivers undertook a variety of activities, though despite pre-experiment encouragement to do so, almost no one brought any materials with them. Thus, the activities included such things as reading the strip map that was in the car, talking to the experimenter, adjusting the radio, and so on. The most frequent activity was using the laptop computer. A third of the drivers closed their eyes at least once for 5 or more consecutive seconds, with averages of 5.7 and 7.1 times for males and females, respectively. Regarding the information available on the laptop computer, drivers found information about the next exit to be least useful. Information about the driver's current location and the traffic ahead were more useful than next exit information. And information about time to the destination was selected significantly more frequently than the other three types of information. Drivers offered several suggestions for additional information they would like to have available during a trip on the AHS. In the commuter experiment, it was noted, however, that only two drivers brought something to do on the next-to-last trial, a somewhat surprising result in light of the fact that the drivers clearly knew by then that they would have almost half an hour during which they did not have any driving-related responsibilities

Using Model Checking Tools to Triage the Severity of Security Bugs in the Xen Hypervisor

185193

Stark tuning of the charge states of a two-donor molecule in silicon

Gate control of phosphorus donor based charge qubits in Si is investigated using a tight-binding approach. Excited molecular states of P2+ are found to impose limits on the allowed donor separations and operating gate voltages. The effects of surface (S) and barrier (B) gates are analyzed in various voltage regimes with respect to the quantum confined states of the whole device. Effects such as interface ionization, saturation of the tunnel coupling, sensitivity to donor and gate placement are also studied. It is found that realistic gate control is smooth for any donor separation, although at certain donor orientations the S and B gates may get switched in functionality. This paper outlines and analyzes the various issues that are of importance in practical control of such donor molecular systems.Comment: 8 pages, 9 figure

Knowledge intensive 'paper-based' form sketching

This work is supported by a University of Malta Research Grant.The research reported in this paper concerns the ongoing development of a Knowledge Intensive Sketching (KiS) framework through which designers are supported in foreseeing directly from their paper-based sketches the relevant life-cycle consequences of their 'component form' solution concepts. The goal of the KiS framework is to retain the important characteristics of freehand sketching, i.e. pencil and paper, whilst at the same time exploit the benefits of Knowledge Intensive CAD technology for proactively guiding designers in generating life-oriented solutions as from early design.peer-reviewe

Proceedings of Formal Methods in Computer Aided Design, FMCAD 2007

Table of Contents: Preface (p. xx) -- Organizing Committee (p. xxi) -- Program Committee (p. xix) -- Referees (p. xxiv) -- SAT-BASED METHODS -- Exploiting Resolution Proofs to Speed up LTL Vacuity Detection for BMC / by Jocelyn Simmonds, University of Toronto; Jessica Davies, University of Toronto; Arie Gurfinkel, SEI at Carnegie Mellon University; and Marsha Chechik, University of Toronto (p. 3) -- Improved Design Debugging using Maximum Satisfiability / by Sean Safarpour, University of Toronto; Mark Liffiton, University of Michigan; Hratch Mangassarian, University of Toronto; Andreas Veneris, University of Toronto; and Karem Sakallah, University of Michigan (p. 13) -- Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification / by Daher Kaiss, Marcelo Skaba, Ziyad Hanna, and Zurah Khasidashvili, Intel IDC (p. 20) -- Boosting Verification by Automatic Tuning of Decision Procedures / by Frank Hutter, Domagoj Babic, Holger Hoos, and Alan Hu, University of British Columbia (p. 27) -- HIGH-LEVEL SYSTEM ANALYSIS -- Verifying Correctness of Transactional Memories / by Ariel Cohen, New York University; John O’Leary, Intel; Amir Pnueli, New York University; Mark Tuttle, Intel; and Lenore Zuck, University of Illinois at Chicago (p. 37) -- Algorithmic Analysis of Piecewise FIFO Systems / by Naghmeh Ghafari, University of Waterloo; Arie Gurfinkel, Carnegie Mellon University; Nils Klarlund, Google; and Richard Trefler, University of Waterloo (p. 45) -- Transaction Based Modeling and Verification of Hardware Protocol Implementations / by Xiaofang Chen, University of Utah; Steven German, IBM; and Ganesh Gopalakrishnan, University of Utah (p. 53) -- Automating Hazard Checking in Transaction-Level Microarchitecture Models / by Yogesh Mahajan and Sharad Malik, Princeton University (p. 62) -- ABSTRACTION-BASED METHODS -- Computing Abstractions by Integrating BDDs and SMT / by Roberto Cavada, FBK-irst; Alessandro Cimatti, FNK-irst; Anders Franzen, FBK-irst; Kalyanasundaram Krishnamani, TIFR-Mumbai & FBK-irst; Marco Roveri, FBK-irst; and R.K. Shyamasundar, TIFR-Mumbai (p. 69) -- Induction in CEGAR for Detecting Counterexamples / by Chao Wang, Aarti Gupta, and Franjo Ivancic, NEC Labs America (p. 77) -- Lifting Propositional Interpolants to the Word-Level / by Daniel Kroening and Georg Weissenbacher, ETH Zurich (p. 85) -- SOFTWARE ANALYSIS METHODS -- Global Optimization of Compositional Systems / by Fadi Zaraket, John Pape, Adnan Aziz, Margarida Jacome, and Sarfraz Khurshid, University of Texas at Austin (p. 93) -- Cross-Entropy Based Testing / by Hana Chockler, Benny Godlin, Eitan Farchi, and Sergey Novikov, IBM Haifa Research Laboratory (p. 101) -- SYMBOLIC TRAJECTORY EVALUATION -- Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation / by Yan Chen, Yujing He, and Fei Xie, Portland State University; and Jin Yang, Intel (p. 111) -- A Logic for GSTE / by Edward Smith, Oxford University (p. 119) -- Automatic Abstraction in Symbolic Trajectory Evaluation / by Sara Adams, Magnus Bjork, and Tom Melham, Oxford University; and Carl-Johan Seger, Strategic CAD Labs, Intel (p. 127) -- SPECIFICATION THEORY -- A Coverage Analysis for Safety Property Lists / by Koen Claessen, Chalmers University of Technology (p. 139) -- What Triggers a Behavior? / by Orna Kupferman and Yoad Lustig, Hebrew University (p. 146) -- Two-Dimensional Regular Expressions for Compositional Bus Protocols / by Kathi Fisler, WPI Department of Computer Science (p. 154) -- A Quantitative Completeness Analysis for Property-Sets / by Martin Oberkönig, Martin Schickel, and Hans Eveking, Darmstadt University of Technology (p. 158) -- INDUSTRIAL-STRENGTH VERIFICATION -- Automated Extraction of Inductive Invariants to Aid Model Checking / by Michael Case, Alan Mishchenko, and Robert Brayton, University of California, Berkeley (p. 165) -- Checking Safety by Inductive Generalization of Counterexamples to Induction / by Aaron Bradley and Zohar Manna, Stanford University (p. 173) -- Fast Minimum Register Retiming Via Binary Maximum-Flow / by Aaron Hurst, Alan Mishchenko, and Robert Brayton, University of California, Berkeley (p. 181) -- Formal Verification of Partial Good Self-Test Fencing Structures / by Adrian Seigler, Gary Van Huben, and Hari Mony, IBM (p. 188) -- Case Study: Integrating FV and DV within the Verification of Intel® Core ™ Microprocessor / by Alon Flaisher, Alon Gluska, and Eli Singerman, Intel (p. 192) -- REASONING ABOUT PHYSICAL SYSTEMS -- Circuit-Level Verification of a High-Speed Toggle / by Chao Yan and Mark R. Greenstreet, University of British Columbia (p. 199) -- Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs / by Mohamed Zaki, Ghiath Al Sammane, and Sofiene Tahar, Concordia University, Montreal; and Guy Bois, Ecole Polytechnique de Montreal (p. 207) -- Analyzing Gene Relationships for Down Syndrome with Labeled Transitions Graphs / by Neha Rungta, Brigham Young University; Hyrum Carroll, Brigham Young University; Eric Mercer, Brigham Young University; Randall Roper, Indiana University-Purdue University Indianapolis; Mark Clement, Brigham Young University; and Quinn Snell, Brigham Young University (p. 216) -- ADVANCED THEOREM-PROVING APPLICATIONS -- A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware / by Julien Schmaltz, Radboud University Nijmegen (p. 223) -- Modeling Time-Triggered Protocols and Verifying their Real-Time Schedules / by Lee Pike, Galois (p. 231) -- A Mechanized Refinement Framework for Analysis of Custom Memories / by Sandip Ray, University of Texas at Austin; and Jayanta Bhadra, Freescale Semiconductor (p. 239) -- Author Index (p. 243)11-14 November, 2007 in Austin, Texashttp://www.cs.utexas.edu/users/hunt/FMCAD/Computer Science

Proceedings of Formal Methods in Computer-Aided Design, FMCAD 2019

Table of Contents: Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties / by Rohit Dureja, Jason Baumgartner, Alexander Ivrii, Robert Kanzelman and Kristin Yvonne Rozier (p. 1) -- Input Elimination Transformations for Scalable Verification and Trace Reconstruction / by Raj Kumar Gajavelly, Jason Baumgartner, Alexander Ivrii, Robert Kanzelman and Shiladitya Ghosh (p. 10) -- Chasing Minimal Inductive Validity Cores in Hardware Model Checking / by Ryan Berryhill and Andreas Veneris (p. 19) -- Verifying Large Multipliers by Combining SAT and Computer Algebra / by Daniela Kaufmann, Armin Biere and Manuel Kauers (p. 28) -- Unification-based Pointer Analysis without Oversharing / by Jakub Kuderski, Jorge A. Navas and Arie Gurfinkel (p. 37) -- Concurrent Chaining Hash Maps for Software Model Checking / by Freark I. van der Berg and Jaco van de Pol (p. 46) -- Proving Data Race Freedom in Task Parallel Programs with a Weaker Partial Order / by Benjamin Ogles, Peter Aldous and Eric Mercer (p. 55) -- BDD-Based Algorithms for Packet Classification / by Nina Narodytska, Leonid Ryzhyk, Igor Ganichev and Soner Sevinc (p. 64) -- TSNsched: Automated Schedule Generation for Time Sensitive Networking / by Aellison Cassimiro Teixeira Dos Santos, Ben Schneider and Vivek Nigam (p. 69) -- Verification and Synthesis of Symmetric Uni-Rings for Leads-To Properties / by Ali Ebnenasir (p. 78) -- Scalable Translation Validation of Unverified Legacy OS Code / by Amer Tahat, Sarang Joshi, Pronnoy Goswami and Binoy Ravindran (p. 87) -- Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity / by Faria Kalim, Karl Palmskog, Jayasi Mehar, Adithya Murali, Indranil Gupta and P. Madhusudan (p. 96) -- KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design / by Luca Piccolboni, Giuseppe Di Guglielmo and Luca Carloni (p. 105) -- Verification of Authenticated Firmware Loaders / by Sujit Kumar Muduli, Pramod Subramanyan and Sayak Ray (p. 110) -- Learning-Based Synthesis of Safety Controllers / by Daniel Neider and Oliver Markgraf (p. 120) -- Shield Synthesis for Real: Enforcing Safety in Cyber-Physical Systems / by Meng Wu, Jingbo Wang, Jyotirmoy Deshmukh and Chao Wang (p. 129) -- Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications / by Gideon Geier, Philippe Heim, Felix Klein and Bernd Finkbeiner (p. 138) -- Synthesizing Reactive Systems Using a Robustness Specification / by Roderick Bloem, Hana Chockler, Masoud Ebrahimi and Ofer Strichman (p. 147) -- Property Directed Inference of Relational Invariants / by Dmitry Mordvinov and Grigory Fedyukovich (p. 152) -- Knowledge Compilation for Boolean Functional Synthesis / by S. Akshay, Jatin Arora, Supratik Chakraborty, Krishna S, Divya Raghunathan and Shetal Shah (p. 161) -- Verifying Relational Properties using Trace Logic / by Gilles Barthe, Renate Eilers, Pamina Georgiou, Bernhard Gleiss, Laura Kovacs and Matteo Maffei (p. 170) -- Autarkies for DQCNF / by Oliver Kullmann and Ankit Shukla (p. 179) -- Localizing Quantifiers for DQBF / by Aile Ge-Ernst, Christoph Scholl and Ralf Wimmer (p. 184) -- Anytime Weighted MaxSAT with Improved Polarity Selection and Bit-Vector Optimization / by Alexander Nadel (p. 193) -- GuidedSampler: Coverage-guided Sampling of SMT Solutions / by Rafael Dutra, Jonathan Bachrach and Koushik Sen (p. 203) -- Extending enumerative function synthesis via SMT-driven classification / by Haniel Barbosa, Andrew Reynolds, Daniel Larraz and Cesare Tinelli (p. 212) -- Proving Non-Termination via Loop Acceleration / by Florian Frohn and Jürgen Giesl (p. 221)Computer Science

Proceedings of Formal Methods in Computer Aided Design, FMCAD 2009

Table of Contents: Preface (p. v) -- Organizing Committee (p. vii) -- Program Committee (p. vii) -- Referees (p. ix) -- Keynote Presentations (p. x) -- Tutorials (p. xii) -- Industrial Experience Reports (p. xiv) -- Panels (p. xvii) -- Session 1. Model Checking -- Interpolation-Sequence Based Model Checking / by Yakir Vizel and Orna Grumberg, The Technion (p. 1) -- Structure-Aware Computation of Predicate Abstraction / by Alessandro Cimatti, FBK-irst; Jori Dubrovin, Helsinki University of Technology; Tommi Junttila, Helsinki University of Technology; and Marco Roveri, FBK-irst (p. 9) -- Enhanced Verification by Temporal Decomposition / by Michael L. Case, Hari Mony, Jason Baumgartner, and Robert Kanzelman, IBM (p. 17) -- Session 2. Software Verification -- Software Model Checking via Large-Block Encoding / by Dirk Beyer, Simon Fraser University; Alessandro Cimatti, FBK-irst; Alberto Griggio, University of Trento & Simon Fraser University; M. Erkan Keremoglu, Simon Fraser University; and Roberto Sebastiani, University of Trento (p. 25) -- Verification of Recursive Methods on Tree-like Data Structures / by Jyotirmoy Deshmukh and E. Allen Emerson, University of Texas at Austin (p. 33) -- MCC: A Runtime Verification Tool for MCAPI User Applications / by Subodh Sharma and Ganesh Gopalakrishnan, University of Utah; Eric Mercer, Brigham Young University; and Jim Holt, Freescale Semiconductor (p. 41) -- Session 3. Satisfiability Modulo Theory -- Generalized and Efficient Array Decision Procedures / by Leonardo de Moura and Nikolaj Bjørner, Microsoft Research (p. 45) -- Decision Diagrams for Linear Arithmetic / by Sagar Chaki and Arie Gurfinkel, SEI/CMU; Ofer Strichman, Technion (p. 53) -- Efficient Decision Procedure for Non-linear Arithmetic Constraints using CORDIC / by Malay Ganai and Franjo Ivančić, NEC Laboratories America (p. 61) -- Mixed Abstractions for Floating-Point Arithmetic / by Angelo Brillout, ETH Zurich; Daniel Kroening and Thomas Wahl, Oxford University (p. 69) -- Session 4. Games -- Safety First: A Two-Stage Algorithm for LTL Games / by Saqib Sohail and Fabio Somenzi, University of Colorado at Boulder (p. 77) -- Synthesizing Robust Systems / by Roderick Bloem and Karin Greimel, Graz University of Technology; Thomas Henzinger, EPFL & IST Austria; Barbara Jobstmann, EPFL (p. 85) -- Session 5. Quantitative Reasoning -- Formal Verification of Analog Designs Using MetiTarski / by William Denman, Behzad Akbarpour, and Sofiène Tahar, Concordia University, Montreal; Mohamed H. Zaki, University of British Columbia; and Lawrence Paulson, University of Cambridge (p. 93) -- Formal Verification of Correctness and Performance of Random Priority-based Arbiters / by Krishnan Kailas, IBM T.J. Watson Research Center; Viresh Paruthi and Brian Monwai, IBM Systems & Technology Group (p. 101) -- Session 6. Assume Guarantee Reasoning -- Assume-Guarantee Validation for STE Properties within an SVA Environment / by Zurab Khasidashvili and Gavriel Gavrielov, Intel Israel; and Tom Melham, Oxford University (p. 108) -- Data Mining Based Decomposition for Assume-Guarantee Reasoning / by He Zhu and Fei He, Tsinghua University; William N. N. Hung, Synopsys; Xiaoyu Song, Portland State University; and Ming Gu, Tsinghua University (p. 116) -- Session 7. Equivalence Checking -- Scalable Conditional Equivalence Checking: An Automated Invariant-Generation Based Approach / by Jason Baumgartner, Hari Mony, and Michael Case, IBM Systems & Technology Group; Jun Sawada, IBM Austin Research Laboratory; and Karen Yorav, IBM Haifa (p. 120) -- Verifying Equivalence of Memories Using a First Order Logic Theorem Prover / by Zurab Khasidashvili and Mahmoud Kinanah, Intel Israel; and Andrei Voronkov, University of Manchester (p. 128) -- A Compositional Theory for Post-Reboot Observational Equivalence Checking of Hardware / by Zurab Khasidashvili, Daher Kaiss, and Doron Bustan, Intel Israel (p. 136) -- Session 8. Debugging -- Scaling VLSI Design Debugging with Interpolation / by Brian Keng and Andreas Veneris, University of Toronto (p. 144) -- Debugging Formal Specifications Using Simple Counterstrategies / by Robert Könighofer, Georg Hofferek, and Roderick Bloem, Graz University of Technology (p. 152) -- Connecting Pre-silicon and Post-silicon Verification / by Sandip Ray and Warren Hunt, University of Texas at Austin (p. 160) -- Session 9. Case Studies and Verification in the Large -- A Verified Platform for a Gate-Level Electronic Control Unit / by Sergey Tverdyshev, Saarland University (p. 164) -- Protocol Verification Using Flows: An Industrial Experience / by John O’Leary, Murali Talupur, and Mark Tuttle, Intel (p. 172) -- Industrial Strength Refinement Checking / by Jesse Bingham, John Erickson, Gaurav Singh, and Flemming Andersen, Intel (p. 180) -- Towards a Formally Verified Network-on-Chip / by Tom van den Broek and Julien Schmaltz, Radboud University Nijmegen (p. 184) -- Hardware/Software Co-Verification of Cryptographic Algorithms using Cryptol / by Levent Erkök, Magnus Carlsson, and Adam Wick, Galois, Inc. (p. 188) -- Session 10. Synthesis -- Retiming and Resynthesis with Sweep Are Complete for Sequential Transformation / by Hai Zhou, Northwestern University (p. 192) -- SAT-Based Synthesis of Clock Gating Functions Using 3-Valued Abstraction / by Eli Arbel, Oleg Rokhlenko, and Karen Yorav, IBM Haifa (p. 198) -- Finding Heap-Bounds for Hardware Synthesis / by Byron Cook, MSR; Ashutosh Gupta, MPI-SWS; Stephen Magill, CMU; Andrey Rybalchenko, MPI-SWS; Jiri Simsa, CMU; Satnam Singh, MSR; and Viktor Vafeiadis, MSR (p. 205) -- Author Index (p. 213)15-18 November, 2009 in Austin, TexasIEEE, IBM, Intel, Jasper Design Automation, NEC Labs America, NVIDIAhttp://www.cs.utexas.edu/users/hunt/FMCAD/Computer Science