Negative-bias-temperature-instability and hot carrier effects in nanowire junctionless p-channel multigate transistors

Negative-bias-temperature-instability (NBTI) and hot-carrier induced device degradation have been experimentally compared between accumulation mode (AM) p-channel multigate transistors (pMuGFETs) and junctionless (JL) pMuGFET. NBTI degradation is less significant in junctionless pMuGFETs than AM pMuGFETs. The threshold voltage shift is less significant in junctionless transistors than AM transistors. The device simulation shows that the peak of lateral electric field and the impact ionization rate of AM device are larger than those of junctionless devices. (C) 2012 American Institute of Physics. (doi:10.1063/1.3688245

Simulation of junctionless Si nanowire transistors with 3 nm gate length

Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of similar to 1 nm wire diameter and similar to 3 nm gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration. (C) 2010 American Institute of Physics. (doi:10.1063/1.3478012

Low-temperature conductance oscillations in junctionless nanowire transistors

Junctionless nanowire transistors show more marked oscillations conductance oscillations than inversion-mode devices. These oscillations can be observed at higher temperature, drain voltage, and gate voltage than in surface-channel, inversion-mode multigate metal-oxide-semiconductor field-effect devices. Clear oscillations are observed at 77 K at a drain voltage of 100 mV in devices with a 10 x 10 nm(2) cross section. (C) 2010 American Institute of Physics. (doi:10.1063/1.3506899

Improvement of carrier ballisticity in junctionless nanowire transistors

In this work we show that junctionless nanowire transistor (JNT) exhibits lower degree of ballisticity in subthreshold and higher ballisticity above threshold compare to conventional inversion-mode transistors, according to quantum mechanical simulations. The lower degradation of the ballisticity above threshold region gives the JNT near-ballistic transport performance and hence a high current drive. On the other hand, lower ballisticity in subthreshold region helps reducing the off-current and improves the subthreshold slope. A three-dimensional quantum mechanical device simulator based on the nonequilibrium Green's function formalism in the uncoupled mode-space approach has been developed to extract the physical parameters of the devices. (C) 2011 American Institute of Physics. (doi:10.1063/1.3559625

Characterization of a junctionless diode

A diode has been realised using a silicon junctionless (JL) transistor. The device contains neither PN junction nor Schottky junction. The device is measured at different temperatures. The characteristics of the JL diode are essentially identical to those of a regular PN junction diode. The JL diode has an on/off current ratio of 10(8), an ideality factor of 1.09, and a reverse leakage current of 1 x 10(-14) A at room temperature. The mechanism of the leakage current is discussed using the activation energy (E-A). The turn-on voltage of the device can be tuned by JL transistor threshold voltage. (C) 2011 American Institute of Physics. (doi: 10.1063/1.3608150

Field-effect mobility extraction in nanowire field-effect transistors by combination of transfer characteristics and random telegraph noise measurements

A technique based on the combined measurements of random telegraph-signal noise amplitude and drain current vs. gate voltage characteristics is proposed to extract the channel mobility in inversion-mode and accumulation-mode nanowire transistors. This method does not require the preliminary knowledge of the gate oxide capacitance or that of the channel width. The method accounts for the presence of parasitic source and drain resistance effect. It has been used to extract the zero-field mobility and the field mobility reduction factor in inversion-mode and junctionless transistors operating in accumulation mode. (C) 2011 American Institute of Physics. (doi:10.1063/1.3626038

Random telegraph-signal noise in junctionless transistors

Random telegraph-signal noise (RTN) is measured in junctionless metal-oxide-silicon field-effect transistors (JL MOSFETs) as a function of gate and drain voltage and temperature. It is shown that the RTN in JL MOSFETs increases significantly when an accumulation layer is formed. The amplitude of RTN is considerably smaller in JL devices than in inversion-mode MOSFET fabricated using similar fabrication parameters. A measurement technique is developed to extract the main parameters of the traps, including the average charge capture and emission time from the traps. (C) 2011 American Institute of Physics. (doi:10.1063/1.3557505

Low-frequency noise in junctionless multigate transistors

Low-frequency noise in n-type junctionless multigate transistors was investigated. It can be well understood with the carrier number fluctuations whereas the conduction is mainly limited by the bulk expecting Hooge mobility fluctuations. The trapping/release of charge carriers is related not only to the oxide-semiconductor interface but also to the depleted channel. The volume trap density is in the range of 6-30 x 10(16) cm(-3) eV(-1), which is similar to Si-SiO2 bulk transistors and remarkably lower than in high-k transistors. These results show that the noise in nanowire devices might be affected by additional trapping centers. (C) 2011 American Institute of Physics. (doi:10.1063/1.3569724

Accurate Characterization of Silicon-On-Insulator MOSFETs for the Design of Low-Voltage, Low-Power RF Integrated Circuits

The maturation of low cost Silicon-on-Insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in-situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static small-signal model and the high-frequency noise parameters for MOSFETs. The extracted model is shown to be valid up to 40 GHz.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/44055/1/10470_2004_Article_271487.pd