A CMOS dynamic random access architecture for radio-frequency readout of quantum devices

As quantum processors become more complex, they will require efficient interfaces to deliver signals for control and readout while keeping the number of inputs manageable. Complementary metal–oxide–semiconductor (CMOS) electronics offers established solutions to signal routing and dynamic access, and the use of a CMOS platform for the qubits themselves offers the attractive proposition of integrating classical and quantum devices on-chip. Here, we report a CMOS dynamic random access architecture for readout of multiple quantum devices operating at millikelvin temperatures. Our circuit is divided into cells, each containing a control field-effect transistor and a quantum dot device, formed in the channel of a nanowire transistor. This set-up allows selective readout of the quantum dot and charge storage on the quantum dot gate, similar to one-transistor–one-capacitor (1T-1C) dynamic random access technology. We demonstrate dynamic readout of two cells by interfacing them with a single radio-frequency resonator. Our approach provides a path to reduce the number of input lines per qubit and allow large-scale device arrays to be addressed

Rapid cryogenic characterisation of 1024 integrated silicon quantum dots

Quantum computers are nearing the thousand qubit mark, with the current focus on scaling to improve computational performance. As quantum processors grow in complexity, new challenges arise such as the management of device variability and the interface with supporting electronics. Spin qubits in silicon quantum dots are poised to address these challenges with their proven control fidelities and potential for compatibility with large-scale integration. Here, we demonstrate the integration of 1024 silicon quantum dots with on-chip digital and analogue electronics, all operating below 1 K. A high-frequency analogue multiplexer provides fast access to all devices with minimal electrical connections, enabling characteristic data across the quantum dot array to be acquired in just 5 minutes. We achieve this by leveraging radio-frequency reflectometry with state-of-the-art signal integrity, reaching a minimum integration time of 160 ps. Key quantum dot parameters are extracted by fast automated machine learning routines to assess quantum dot yield and understand the impact of device design. We find correlations between quantum dot parameters and room temperature transistor behaviour that may be used as a proxy for in-line process monitoring. Our results show how rapid large-scale studies of silicon quantum devices can be performed at lower temperatures and measurement rates orders of magnitude faster than current probing techniques, and form a platform for the future on-chip addressing of large scale qubit arrays.Comment: Main text: 14 pages, 8 figures, 1 table Supplementary: 8 pages, 6 figure

Spin Readout of a CMOS Quantum Dot by Gate Reflectometry and Spin-Dependent Tunneling

International audienceSilicon spin qubits are promising candidates for realizing large-scale quantum processors, benefitting from a magnetically quiet host material and the prospects of leveraging the mature silicon device fabrication industry. We report the measurement of an electron spin in a singly occupied gate-defined quantum dot, fabricated using CMOS-compatible processes at the 300-mm wafer scale. For readout, we employ spin-dependent tunneling combined with a low-footprint single-lead quantum-dot charge sensor, measured using rf gate reflectometry. We demonstrate spin readout in two devices using this technique, obtaining valley splittings in the range 0.5–0.7 meV using excited-state spectroscopy, and measure a maximum electron-spin relaxation time (T1) of 9 ± 3 s at 1 T. These long lifetimes indicate the silicon-nanowire geometry and fabrication processes employed here show a great deal of promise for qubit devices, while the spin-readout method demonstrated here is well suited to a variety of scalable architecture