First Measurements of a Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for Extreme Rate HEP Detectors at HL-LHC

A first prototype of a readout ASIC in CMOS 65nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50x50 um2 and the matrix consists of 64x64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35x35 um2. ENC value is below 100e- for an input capacitance of 50 fF and in-time threshold below 1000e-. Leakage current compensation up to 50 nA with power consumption below 5 uW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 us. The total power consumption per pixel is below 5uW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper

BASIC32: A New ASIC for Silicon Photomultiplier Detectors

Silicon Photomultipliers (SiPM) have shown to be excellent substitutes for more traditional and bulky Photomultiplier Tubes (PMT) in many photon detection applications, thanks essentially to their high quantum efficiency, lowbias voltage and immunity to magnetic fields.However, they pose some challenging design constraints on the design of the electronic front-end (FE) due to their intrinsic high gain and speed. In particular, when changing from low to high light levels of exposition, they produce output signals whose amplitude may span over about three order of magnitude with rise times of less than 1 ns. This is of particular concern when developing integrated multichannel electronics in deep submicron technology. We report here on the realization of a 32-channel ASIC in CMOS technology, based on an innovative current-mode architecture. Besides presenting the experimental results of the ASIC characterization, some perspective indications are given concerning the work currently in progress

Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades

RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm2) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments