44 research outputs found

    The Physics of the B Factories

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    Implementation of Propeller Simulation Techniques at DNW

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    Transport of Colloidal Particles in Microscopic Porous Medium Analogues with Surface Charge Heterogeneity: Experiments and the Fundamental Role of Single-Bead Deposition

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    Understanding colloid transport in subsurface environments is challenging because of complex interactions among colloids, groundwater, and porous media over several length scales. Here, we report a versatile method to assemble bead-based microfluidic porous media analogues with chemical heterogeneities of different configurations. We further study the transport of colloidal particles through a family of porous media analogues that are randomly packed with oppositely charged beads with different mixing ratios. We recorded the dynamics of colloidal particle deposition at the level of single grains. From these, the maximum surface coverage (theta(max) = 0.051) was measured directly. The surface-blocking function and the deposition coefficient (k(pore) = 3.56 s(-1)) were obtained. Using these pore-scale parameters, the transport of colloidal particles was modeled using a one-dimensional advection-dispersion-deposition equation under the assumption of irreversible adsorption between oppositely charged beads and colloids, showing very good agreement with experimental breakthrough curves and retention profiles at the scale of the entire porous medium analogue. This work presents a new approach to fabricate chemically heterogeneous porous media in a microfluidic device that enables the direct measurement of pore-scale colloidal deposition. Compared with the conventional curve-fitting method for deposition constant, our approach allows quantitative prediction of colloidal breakthrough and retention via coupling of direct pore-scale measurements and an advection-dispersion-deposition model.11Nsciescopu

    Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends

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    Designing memory controllers for complex real-time and high-performance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories, while the second identifies challenges in providing DRAM access to memory clients with mixed time-criticality. The third presentation proposes an integrated approach to optimize cost and performance of the DRAM subsystem, and the last one describes how wide DRAM interfaces enabled by 3D technology improve DRAM performance and reduces power
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