Simplified vector-thread architectures for flexible and efficient data-parallel accelerators

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 165-170).This thesis explores a new approach to building data-parallel accelerators that is based on simplifying the instruction set, microarchitecture, and programming methodology for a vector-thread architecture. The thesis begins by categorizing regular and irregular data-level parallelism (DLP), before presenting several architectural design patterns for data-parallel accelerators including the multiple-instruction multiple-data (MIMD) pattern, the vector single-instruction multiple-data (vector-SIMD) pattern, the single-instruction multiple-thread (SIMT) pattern, and the vector-thread (VT) pattern. Our recently proposed VT pattern includes many control threads that each manage their own array of microthreads. The control thread uses vector memory instructions to efficiently move data and vector fetch instructions to broadcast scalar instructions to all microthreads. These vector mechanisms are complemented by the ability for each microthread to direct its own control flow. In this thesis, I introduce various techniques for building simplified instances of the VT pattern. I propose unifying the VT control-thread and microthread scalar instruction sets to simplify the microarchitecture and programming methodology. I propose a new single-lane VT microarchitecture based on minimal changes to the vector-SIMD pattern.(cont.) Single-lane cores are simpler to implement than multi-lane cores and can achieve similar energy efficiency. This new microarchitecture uses control processor embedding to mitigate the area overhead of single-lane cores, and uses vector fragments to more efficiently handle both regular and irregular DLP as compared to previous VT architectures. I also propose an explicitly data-parallel VT programming methodology that is based on a slightly modified scalar compiler. This methodology is easier to use than assembly programming, yet simpler to implement than an automatically vectorizing compiler. To evaluate these ideas, we have begun implementing the Maven data-parallel accelerator. This thesis compares a simplified Maven VT core to MIMD, vector-SIMD, and SIMT cores. We have implemented these cores with an ASIC methodology, and I use the resulting gate-level models to evaluate the area, performance, and energy of several compiled microbenchmarks. This work is the first detailed quantitative comparison of the VT pattern to other patterns. My results suggest that future data-parallel accelerators based on simplified VT architectures should be able to combine the energy efficiency of vector-SIMD accelerators with the flexibility of MIMD accelerators.by Christopher Francis Batten.Ph.D

The padding scheme for RSA signatures

The RSA scheme is used to sign messages; however, in order to avoid forgeries, a message can be padded with a fixed string of data P. De Jonge and Chaum showed in 1985 that forgeries can be constructed if the size of P (measured in bytes) is less than the size of N/3, where N is the RSA modulus. Girault and Misarsky then showed in 1997 that forgeries can be constructed if the size of P is less than the size of N/2. In 2001, Brier, Clavier, Coron and Naccache showed that forgeries can still be constructed when the size of P is less than two thirds the size of N. In this paper, we demonstrate that this padding scheme is always insecure; however, the complexity of actually finding a forgery is O(N). We then focus specifically on the next unsettled case, where P is less than 3/4 the size of N and show that finding a forgery is equivalent to solving a set of diophantine equations. While we are not able to solve these equations, this work may lead to a break-through by means of algebraic number theory techniques

Spatial Distribution of Pleistocene and Holocene Faunal Remains, South Block Excavations

The fossil remains of mammoth and other Pleistocene fauna found along and near the escarpment of the west shore of Lima Reservoir in Centennial Valley have been the subject of field investigations since the 1980s. Summaries or earlier studies conducted at the locality are presented in various published and unpublished sources including Albanese, Davis, and Hill (1995), Bump (1995), Davis and Batten (1996), Dundas (1989, 1990, 1996), Hill and Albanese (1996), and Hill, Davis, and Albanese (1995)

Scale Control Processor Test-Chip

We are investigating vector-thread architectures which provide competitive performance and efficiency across a broad class of application domains. Vector-thread architectures unify data-level, thread-level, and instruction-level parallelism, providing new ways of parallelizing codes that are difficult to vectorize or that incur excessive synchronization costs when multithreaded. To illustrate these ideas we have developed the Scale processor, which is an example of a vector-thread architecture designed for low-power and high-performance embedded systems. The prototype includes a single-issue 32-bit RISC control processor, a vector-thread unit which supports up to 128 virtual processor threads and can execute up to 16 instructions per cycle, and a 32 KB shared primary cache.Since the Scale Vector-Thread Processor is a large and complex design (especially for an academic project), we first designed and fabricated the Scale Test Chip (STC1). STC1 includes a simplified version of the Scale control processor, 8 KB of RAM, a host interface, and a custom clock generator. STC1 helped mitigate the risk involved in fabricating the full Scale chip in several ways. First, we were able to establish and test our CAD toolflow. Our toolflow included several custom tools which had not previously been used in any tapeouts. Second, we were able to better characterize our target package and process. For example, STC1 enabled us to better correlate the static timing numbers from our CAD tools with actual silicon and also to characterize the expected rise/fall times of our external signal pins. Finally, STC1 allowed us to test our custom clock generator. We used our experiences with STC1 to help us implement the Scale vector-thread processor. Scale was taped out on October 15, 2006 and it is currently being fabricated through MOSIS. This report discusses the fabrication of STC1 and presents power and performance results

Peste des Petits Ruminants infection among cattle and wildlife in Northern Tanzania

We investigated peste des petits ruminants (PPR) infection in cattle and wildlife in northern Tanzania. No wildlife from protected ecosystems were seropositive. However, cattle from villages where an outbreak had occurred among small ruminants showed high PPR seropositivity, indicating that spillover infection affects cattle. Thus, cattle could be of value for PPR serosurveillance

Field-Reassortment of Bluetongue Virus Illustrates Plasticity of Virus Associated Phenotypic Traits in the Arthropod Vector and Mammalian Host In Vivo

Reassortment between virus strains can lead to major shifts in the transmission parameters and virulence of segmented RNA viruses, with consequences for spread, persistence, and impact. The ability of these pathogens to adapt rapidly to their environment through this mechanism presents a major challenge in defining the conditions under which emergence can occur

Algorithms for automated DNA assembly

Generating a defined set of genetic constructs within a large combinatorial space provides a powerful method for engineering novel biological functions. However, the process of assembling more than a few specific DNA sequences can be costly, time consuming and error prone. Even if a correct theoretical construction scheme is developed manually, it is likely to be suboptimal by any number of cost metrics. Modular, robust and formal approaches are needed for exploring these vast design spaces. By automating the design of DNA fabrication schemes using computational algorithms, we can eliminate human error while reducing redundant operations, thus minimizing the time and cost required for conducting biological engineering experiments. Here, we provide algorithms that optimize the simultaneous assembly of a collection of related DNA sequences. We compare our algorithms to an exhaustive search on a small synthetic dataset and our results show that our algorithms can quickly find an optimal solution. Comparison with random search approaches on two real-world datasets show that our algorithms can also quickly find lower-cost solutions for large datasets

The effect of temperature on the stability of African swine fever virus BA71V isolate in environmental water samples

African swine fever virus (ASFV) is known to be very stable and can remain infectious over long periods of time especially at low temperatures and within different matrices, particularly those containing animal-derived organic material. However, there are some gaps in our knowledge pertaining to the survivability and infectivity of ASFV in groundwater. This study aims to determine the stability and infectivity of the cell culture-adapted ASFV strain BA71V by plaque assay after incubation of the virus within river water samples at three different environmentally relevant temperatures (4 °C, 15 °C, and 21 °C) over the course of 42 days. The results from this study indicate that ASFV can remain stable and infectious when maintained at 4 °C in river water for more than 42 days, but as incubation temperatures are increased, the stability is reduced, and the virus is no longer able to form plaques after 28 days and 14 days, respectively, when stored at 15 °C and 21 °C. Characterizing the survivability of ASFV in groundwater can allow us to develop more appropriate inactivation and disinfection methods to support disease control and mitigate ASFV outbreaks

Calcineurin/NFAT Signaling in Activated Astrocytes Drives Network Hyperexcitability in A\u3cem\u3eβ\u3c/em\u3e-Bearing Mice

Hyperexcitable neuronal networks are mechanistically linked to the pathologic and clinical features of Alzheimer\u27s disease (AD). Astrocytes are a primary defense against hyperexcitability, but their functional phenotype during AD is poorly understood. Here, we found that activated astrocytes in the 5xFAD mouse model were strongly associated with proteolysis of the protein phosphatase calcineurin (CN) and the elevated expression of the CN-dependent transcription factor nuclear factor of activated T cells 4 (NFAT4). Intrahippocampal injections of adeno-associated virus vectors containing the astrocyte-specific promoter Gfa2 and the NFAT inhibitory peptide VIVIT reduced signs of glutamate-mediated hyperexcitability in 5xFAD mice, measured in vivo with microelectrode arrays and ex vivo brain slices, using whole-cell voltage clamp. VIVIT treatment in 5xFAD mice led to increased expression of the astrocytic glutamate transporter GLT-1 and to attenuated changes in dendrite morphology, synaptic strength, and NMDAR-dependent responses. The results reveal astrocytic CN/NFAT4 as a key pathologic mechanism for driving glutamate dysregulation and neuronal hyperactivity during AD