A Defect-tolerant Cluster in a Mesh SRAM-based FPGA

International audienceIn this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input combinations. While at the interconnect level, fine grain redundancy is introduced which not only bypasses defects but also increases routability. Taking advantage of the sparse intra-cluster interconnect structures, routability is further improved by efficient distribution of feedback paths allowing more flexibility in the connections among logic blocks. Emulation results show a significant improvement of about 15% and 34% in the robustness of logic block and intra-cluster interconnect respectively. Furthermore, the impact of these hardening schemes on the testability of the FPGA cluster for manufacturing defects is also investigated in terms of maximum achievable fault coverage and the respective cost

Mathematical modelling of Logic Locking against the insertion of Hardware Trojan in an Intregated Circuit

International audienc

Improving Integrated Circuit Security using Mathematical Model Based on Clique Covering Reformulation

International audienceIntegrated Circuits (IC) are increasingly present in our daily lives through various everyday objects. Many third-party companies are involved during the manufacturing process. It introduces many threats to the ICs manufacturing, such as IP piracy and Hardware Trojans. Strong Logic Locking methodology is generally used to protect from IC piracy, such as counterfeiting or reverse engineering, and against Hardware Trojans insertion; however, the lack of automated tools fully integrated into a CAD flow limits the integration of countermeasures. This paper proposes mathematical models on the Strong Logic Locking method to optimize the security and an automatic security design inserted in an open CAD flow.We implemented an exact algorithm to maximize the security measure while implementing a strategy to minimize the impact of delay and area on the circuit. This algorithm is a custom branch and bound based on the mathematical model developed in this paper. In addition, we propose a strategy to limit the impact of countermeasures on the delay. Furthermore, our approach takes place inside a standard open CAD flow after logic synthesis to be as generic as possible.The experiments carried out that security can be added in a standard open CAD flow with a reasonable computation time and a limited impact on the circuit. Our security measure is more precise than the previous one, with a limited area overhead defined by a user. The increase of the critical path is less than 7% for large benches with a limit of 10% area overhead

Recherche de cliques pour un problème de cybersécurité matériel

International audienceDans l'objectif de la lutte contre les Chevaux de Troie Matériels, nous proposons d'optimiser une méthode appelé Strong Logic Locking. La mesure de sécurité de cette méthode se base sur les cliques d'un graphe de relation, plus les cliques sont grandes et nombreuses, meilleure sera la sécurité. Nous proposons deux approches pour modéliser et résoudre ce problème

Stratus : Un environnement de développement de circuits

NAT LIP6 CIANNational audienceno abstrac

Stratus : Un environnement de développement de circuits

NAT LIP6 CIANNational audienceno abstrac

RISC-V design using Free Open Source Software

International audienceThis tutorial aims to build a RISC-V processor using only free VLSI CAD tools with a symbolic technology approach (a refined Mead-Conway method as formerly used by MOSIS). The toolchain is currently organized as follow: A design description in VHDL language. Simulation with GHDL. Logical synthesis with Yosys. We use a frontend to convert VHDL into Verilog (from Alliance). Physical design (place & route) using Coriolis. DRC & LVS using Alliance. Timing analysis with Tas & Yagle. Symbolic to real translation (Alliance).Our first objective is to design a RISC-V for AMS 350nm node.The choice of symbolic technology is mainly made for three reasons: Node portability: From one symbolic layout, you may target multiple technologies. Community: Symbolic layout does not contain any NDA related information. As such it can freely be published and shared. Security.:With a published layout, everybody can check that the chip send back from the foundry is exactly what it should be (no hardware trojan)

Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip

International audienceIn this paper, we present the implementation of a multi-threaded software application for pre-crash obstacle detection, using stereo vision, and the "V-disparity" algorithm, that requires intensive computation. This application runs on a generic, low cost, massively parallel, multi-processor system-on-chip (MP-SoC). This hardware architecture is suitable for automotive area with respect to performance, cost, and flexibility constraints. This hardware/software embedded application is able to process 40 stereoscopic pairs per second with 256 lines of 512 pixels images and a disparity range of 256. Our architecture is made of 8 clusters, 30 general-purpose 32-bit processors and 750 Kbytes embedded memory