Titanium Dioxide Modifications for Energy Conversion: Learnings from Dye-Sensitized Solar Cells

During the last two and half decade modifying anatase TiO2 has appreciably enhanced our understanding and application of this semiconducting, non-toxic material. In the domain of DSCs, the main focus has been to achieve band adjustment to facilitate electron injection from anchored dyes, and high electronic mobility for photo-generated electron collection. In retrospection, there is a dire need to assimilate and summarize the findings of these studies to further catalyze the research, better understanding and comparison of the structure–property relationships in modifying TiO2 efficiently for crucial photocatalytic, electrochemical and nanostructured applications. This chapter aims at categorizing the typical approaches used to modify TiO2 in the domain of DSCs such as through TiO2 paste additives, TiO2 doping, metal oxides inclusion, dye solution co-adsorbing additives, post staining surface treatment additives and electrolyte additives. A summary of the consequences of these modifications on electron injection, charge extraction, electronic mobility, conduction band shift and surface states has been presented. This chapter is expected to hugely benefit the researchers employing TiO2 in energy, catalysis and battery applications

Substrate integrated waveguide antenna system for 5G in-band full duplex applications

In-band full duplex offers a new approach of meeting the ever-increasing data rate demands by operating the transmitter and receiver at the same frequency at the same time, potentially doubling the spectral efficiency. However, self-interference is the fundamental bottleneck of such systems. In contrast to non-planar or sub 6 GHz microstrip designs reported so-far, this paper presents an all SIW based antenna system for in-band full duplex systems. The proposed design integrates a dual linear polarized three port differential antenna, three port SIW common-mode power combiner and a 180°phase shifter at 28 GHz. Operating the antenna in TE201 mode provides inherent isolation between the differential receive and single-ended transmit port. The residual coupling is further reduced through use of TE101 based power combiner and a 180°phase shifter. Implemented on a 0.508 mm thick RT Duroid 5880 substrate, the antenna occupies a foot-print of 48 × 80 mm2. Demonstrating a measured gain of 6.95 dBi and 3.42 dBi for Tx and Rx mode of operation, respectively, the proposed design offers a self-interference cancellation (SiC) of better than 36 dB over a 177 MHz bandwidth

Flexible phase-locked loops and millimeter wave PLL components for 60-GHz wireless networks in CMOS

The 60 GHz license-free frequency band offers the possibility of multi-gigabit per second wireless transmission satisfying the increasing demand of data intensive applications over short distances. Over the last decade, aggressive down-scaling of CMOS technologies coupled with an intensive research effort has made the realization of complete 60 GHz systems, a reality. In this work, frequency synthesizers as enabling sub-systems for 60 GHz transceivers have been presented. In order to accomplish an accurately functioning overall system, a systematic top-down approach was adopted which included the system analysis followed by design and implementation of critical synthesizer components and finally their combined integration to form the proposed synthesizer. Experience of the complete design flow at mm-wave frequencies was attained that, apart from circuit design solutions, included specialized layout and measurement techniques. Chapter 2 laid down the system architecture of the synthesizer. The channelization specifications for the synthesizer were extracted from the IEEE 802.15.3c which is a standard still in works. The proposed channels were either based on 2 GHz HRP for data intensive applications or 1 GHz and 500 MHz LRP channels for moderate and low data rate applications, respectively. A flexible synthesizer architecture was proposed with the aim to support a number of potential frequency conversion techniques which can be adopted for a 60 GHz transceiver. While re-using the same back-end and by adopting flexible synthesizer front-ends, the proposed architecture supported the sliding-IF topology and the direct conversion topology with and without a frequency tripler. An overview of synthesizer basics was also included followed by calculations and system level simulations of the overall system. In chapter 3, the impact of layout parasitics and sensitivity of measurements at mm-wave frequencies and the techniques employed in this work to address them were elaborated. For mm-wave layout there are no-rules but only guidelines. Distributed analysis at mm-wave frequencies is not only required due to small wavelengths but also because the interconnect parasitics become of the same order as the passive structures. Therefore, a maximum tolerable interconnect length based on the operation frequency and the circuit application needs to be determined. Furthermore, the circuit floor-planning becomes important and should be done in a way to minimize interconnect lengths. In addition to the usual RC-extraction, EM-solvers need to be utilized for critical interconnects for inductance extraction. In order to reduce substrate losses, cross-talk and coupling between components, shielding techniques such as meshed grounding, coplanar transmission lines, and guard-rings should be utilized. The second half of chapter 3 was dedicated to mm-wave IC measurement issues such as losses, mismatches and variation in the equipment, cables, connectors, probe position and temperature. In general, the measurement plane has to be shifted close to the DUT by performing accurate and regular calibrations. Furthermore, the measurement environment should be kept quiet to avoid external noise corrupting the on-chip signals. To obtain stable and repeatable results, physical change in the setups must be avoided and a considerable number of samples should be measured to average out the unwanted contributions in the measured results. Chapter 4 focused on the synthesizer front-end components which operate at the highest frequencies in the synthesizer and are the most challenging blocks. A step wise approach was adopted, starting with individual component design of the prescalers and VCOs and concluding with an integrated front-end. An overview of different prescaler architectures revealed that static and dynamic frequency dividers are easy to design and provide wide locking range; however, they fall short of reaching close to 60 GHz. Injection locked frequency dividers, on the other hand, are able to operate at mm-wave frequencies but their narrow-band nature results in smaller locking range. Thus, circuit design techniques have been adopted to improve the latter characteristic. Three examples of injection locked frequency dividers were presented. The 40 GHz divide-by-2 quadrature ILFD based on direct injection used an input power matching technique by utilizing interconnect inductance to cancel-out parasitic capacitance of the injection transistor. This enhanced the injection efficiency and resulted in a wide locking range. The 60 GHz divide-by-3 ILFD on the other hand addressed the locking range issue by adopting harmonic enhancement through resistive feedback. The last prescaler presented for the proposed synthesizer combined the divide-by-2 and divide-by-3 operations in one circuit, thus simplifying the overall system architecture considerably. New figure-of-merits were introduced for frequency dividers for a proper comparison especially between ILFDs with or without varactor tuning. The introduced FOMs also incorporated the DC power consumption and input sensitivity, which are important performance benchmarks for ILFDs. The second major section of chapter 4 was dedicated to the voltage controlled oscillator. An overview of various VCO architectures was presented among which LC based VCOs were found to be suitable for 60 GHz frequency operation with reasonable tuning range and phase noise. Three LC-VCO circuits were presented next. The VCO for the 40 GHz front-end was a complementary cross-coupled structure and employed differential tuning for the capacitive tuning circuit. Two I-Q VCOs for the 60 GHz synthesizer front-end were presented next. The first was based on active coupling using transistors whereas the second was based on passive coupling using on-chip transformers. The transformer was measured as a separate test-structure and provided reasonable between EM simulations and measurements. By way of analysis, it was found that a dual-band VCO (operating at 40 and 60 GHz) utilizing switches and with satisfactory FTR was very difficult to achieve. This was because either the losses of the switch were too high, which degraded the tank Q-factor, or the fixed capacitance added to the tank was too large, which decreased the tuning range. Therefore, two separate VCOs operating at the aforementioned frequencies were adopted as a way-forward for synthesizer front-end integration. The last section of chapter 4 presented the integrated synthesizer front-ends at 40 and 60 GHz which was an important step towards complete system integration. The main challenge in combining the two front-end components was to align their operating ranges. In chapter 5, the synthesizer back-end components including the low frequency dividers, phase frequency detector, charge pump and loop filter were presented. Although working at lower frequencies, these components entailed challenges such as accuracy, matching and robustness. Two approaches for feedback division namely cascaded divide-by-2 stages and mixer based division were demonstrated. The former was optimized for low power consumption by reducing the transistor dimensions and moderately increasing the load resistors. The mixer based approach offered further reduction of power consumption; however, it required a fixed and accurate LO for down-converting the ILFD output to a frequency close to the reference frequency of the synthesizer. The PFD, based on D-flip-flops, was constructed by custom made NAND gates and the dead-zone was eliminated by inserting intentional delay in the reset path. The charge-pump was optimized for matching between up and down currents and voltage drops across transistors were equalized by using dummy transistors. The second order loop filter was combined with the PFD and charge-pump to determine the response of the back-end to increasing or decreasing phase and frequency difference. Finally in chapter 6, building on the components and sub-circuit designs of preceding chapters, complete synthesizers based on our proposed flexible architecture were presented. Using the expertise from chapter 4 of VCO, ILFD and front-end design, the integration of the complete 40 GHz synthesizer was considerably simplified and the measured and simulated results matched very closely. Based on the 40 GHz components, a single-mode synthesizer for 60 GHz sliding-IF system was presented first. It demonstrated sufficient locking range to cover the 60 GHz frequency band from 57 to 65 GHz. Furthermore, the measured phase noise, settling time and power consumption were comparable to the state-of-the-art published synthesizers. The next synthesizer replaced the divider chain in the feedback loop with a mixer operated by an external LO signal. For testing purposes, the reference frequency was fixed and the output of the synthesizer was set by varying the mixer LO frequency. At simulation level, this setup offered savings in silicon area and power consumption. However, it had a drawback of an extra LO frequency. Finally, a dual-mode synthesizer matching the proposed architecture was presented which included the 40 and 60 GHz VCOs, both connected to a single dual-mode ILFD. In the 60 GHz direct-conversion mode, the tuning-range of the VCO was found to be a limiting factor and the presented design could only cover eleven out of twelve 500 MHz LRP channels. Combining the performance parameters of the two individual synthesizers, the dual-mode synthesizer provides an elegant solution for sliding-IF as well as direct-conversion transceivers with or without using a frequency tripler

Harnessing Photovoltage: Effects of Film Thickness, TiO₂ Nanoparticle Size, MgO and Surface Capping with DSCs

High photovoltage dye-sensitized solar cells (DSCs) offer an exceptional opportunity to power electrocatalysts for the production of hydrogen from water and the reduction of CO₂ to usable fuels with a relatively cost-effective, low-toxicity solar cell. Competitive recombination pathways such as electron transfer from TiO₂ films to the redox shuttle or oxidized dye must be minimized to achieve the maximum possible photovoltage (<i>V</i>_oc) from DSC devices. A high <i>V</i>_oc of 882 mV was achieved with the iodide/triiodide redox shuttle and a ruthenium NCS-ligated dye, <b>HD-2-mono</b>, by utilizing a combined approach of (1) modulating the TiO₂ surface area through film thickness and nanoparticle size selection, (2) addition of a MgO insulating layer, and (3) capping available TiO₂ film surface sites post film sensitization with an F-SAM (fluorinated self-assembled monolayer) treatment. The exceptional <i>V</i>_oc of 882 mV observed is the highest achieved for the popular NCS containing ruthenium sensitizers with >5% PCE and compares favorably to the 769 mV value observed under common device preparation conditions

RF Energy Harvesting for Ubiquitous, Zero Power Wireless Sensors

This paper presents a review of wireless power transfer (WPT) followed by a comparison between ambient energy sources and an overview of different components of rectennas that are used for RF energy harvesting. Being less costly and environment friendly, rectennas are used to provide potentially inexhaustible energy for powering up low power sensors and portable devices that are installed in inaccessible areas where frequent battery replacement is difficult, if not impossible. The current challenges in rectenna design and a detailed comparison of state-of-the-art rectennas are also presented

A 40-GHz Phase-Locked Loop Front-End for 60-GHz Transceivers in 65nm CMOS

A phase-locked loop front-end including a LC voltage controlled oscillator and an I-Q injection locked frequency divider is presented. The operation ranges of the VCO and ILFD are aligned by co-designing the tank, specifically the tunable varactors. The total locking range of the front-end is 37.6 to 42.2 GHz which corresponds to a down-conversion range from 56.4 to 63.3 GHz at 60 GHz, thus covering the complete ISM band. The front-end phase noise for a VCO frequency of 39.8 GHz is -102 dBc/Hz at 1 MHz offset. The DC power consumption of the VCO and Q-ILFD is 6mW and 9mW from a 1.2 V supply, respectively. Implemented in a bulk CMOS 65nm technology, the circuit occupies an area of 0.7 × 0.5 mm2

Quad-Band 3D Rectenna Array for Ambient RF Energy Harvesting

This paper presents a quad-band, 3D mountable rectenna module for ambient energy harvesting. With the aim of powering up Internet of Things (IoT) nodes in practical ambient environments, a hybrid approach of combining power, both at RF and DC, is adopted using 98 MHz FM band, GSM900 (Global System for Mobile Communications), GSM1800, and Wi-Fi 2.4 GHz band. A dual polarized cross-dipole antenna featuring asymmetric slots as well as central ring structure enables multiband response and improved matching at the higher three frequency bands, whereas a loaded monopole wire antenna is used at the lower FM band. Four identical multiband antennas are placed in a 3D cubic arrangement that houses a 4-to-1 power combiner and matching circuits on the inside and the FM antenna on the top. In order to maintain stable rectenna output at varying input power levels and load resistances, a novel transmission line based matching network using closed form equations is proposed. Integrated in form of a 10 × 10 × 10 cm3 cube using standard FR4 substrate, the rectenna generates a peak output voltage of 2.38 V at −10 dBm input power. The RF to DC conversion efficiency is 70.28%, 41.7%, 33.37%, and 27.69% at 98 MHz, 0.9 GHz, 1.8 GHz, and 2.4 GHz, respectively, at −6 dBm. The rectenna also exhibits a measured conversion efficiency of 31.3% at −15 dBm for multitone inputs in ambient environment. The promising results in both indoor and outdoor settings are suitable to power low power IoT devices

A 40-GHz phase-locked loop for 60-GHz sliding-IF transceivers in 65nm CMOS

This paper presents a 40 GHz phase-locked loop as an enabling component for sliding-IF 60 GHz transceivers. The PLL front-end includes, a 40 GHz LC voltage controlled oscillator (VCO) and a quadrature injection locked frequency divider (ILFD), which are tuned simultaneously to align their tuning and locking range, respectively. The PLL back-end consists of an optimized divider chain, PFD, CP and a second-order passive loop filter integrated on chip. The PLL can be locked from 38.2 to 43.6 GHz corresponding to a down-conversion range of 57.3 to 65.4 GHz, thus covering all IEEE 802.15.3c channels. The phase noise for a 40.2 GHz output is - 89.7, -94 and -112 dBc/Hz at 1 MHz, 4 MHz and 10 MHz offsets, respectively. The settling time is lower than 2μsec and reference spurs are lower than -42dB. Implemented in a 65nm bulk CMOS technology, the PLL consumes 22.8 mW, excluding buffers, from a 1.2 V supply and occupies 1.67×0.745 mm2 silicon area