Stacked CMOS Technologies

Stacking metal-oxide semiconductor field-effect transistors on top of each other to form multilayer integrated circuits (ICs) is an effective way to reduce footprint and interconnect distance. In term of topology, stacked complementary metal-oxide semiconductor (CMOS) technologies can be classified into two major categories: One that has the active devices and interconnects interleaving each other, One that has the active device layers and interconnects grouped separately

Reduction of interconnect loading in sub-100nm technology by 3D stacked-FinCMOS

The paper describes a stacked-FinCMOS technology to form high density 3D integrated circuits with local clusters. Circuit design with the described process can utilize the mature 2D design methodology and software with minimal modifications. Standard cells and other building blocks have been designed with the stacked-FinCMOS technology. Preliminary results show that the described process can effectively increase the circuit density, reduce the capacitive loading, and at the same time maintain a reasonable heat dissipation

A CMOS Active-Pixel Sensor Based DNA Micro-Array with Nano-Metallic Particles Detection Protocol

A DNA Micro-Array based on integrated CMOS Active Pixel Sensor utilizing the opacity of self-assembled nano-metallic particles is demonstrated Due to the complementary nature of DNA hybridization process, the DNA fragments attached to the nano-particle precipitate them only at locations where complementary DNA strands exist. The opacity of the chip surface change due to accumulation of nano-metallic particles can be used to defect the existence of some targeted DNA fragments Ordinary light sources can be used in this approach rather than special UV light sources in the most popular fluorescence based detection method The chip has been fabricated with a 0.5 mu m CMOS process and contains on-chip timing control, dynamic range enhancement by pulse-width modulation and correlated double sampling. The system can detect DNA sample with extremely low concentration down to 16pM under

Tunneling field effect transistor technology

This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency. · Provides comprehensive reference to tunneling field effect transistors (TFETs); · Covers all aspects of TFETs, from device process to modeling and applications; · Enables design of power-efficient integrated circuits, with low power consumption TFETs

Reduction of ambipolarity in carbon nanotube field-effect transistor by non-uniform source/drain doping and increased extension length

The effect of non-degenerate doping on the ambipolarity of a conventional carbon nanotube field effect transistor (C-CNFET) is investigated in this paper together with different source/drain extension lengths. The ambipolarity ratio for C-CNFET can be reduced by eight orders of magnitude, by using reduced doping levels and increased extension lengths, at the cost of one order of magnitude reduction in on-state current