On board Processor and Processing Strategies for Next Generation Reconfigurable Satellite Payloads

Today, the increasing demand in higher data rates necessitates new methods as well as higher flexibility for satellite telecommunication payloads in order to address a variety of applications and customers. This paper presents one of these processing strategies that is applicable to today’s processing satellite payloads aiming to meet those demands. For this purpose, a two-tier filter bank is designed as part of a digital onboard processor, which first divides the spectrum at the output of the ADC into a number of sub-bands extracting all the stacked channels in the digital domain. Following the analysis section of the first tier of operations, the extracted channels go under a secondary channelisation process to obtain much finer granularity of 31.25 kHz or 50 kHz depending on the communication standard used for data transmission. The implementation of the channeliser was delivered on a bit-true simulation model and the input and the output of the channelisers were compared and evaluated both in the time and frequency domains

Nonlinear Phase Filtering Effects on GNSS Receiver Positioning Accuracy

This paper demonstrates nonlinear phase filtering effects on GNSS receiver accuracy. Using a nonlinear phase filter in a GNSS receiver can change the pseudorange estimation up to 250 metres which introduces an error in the overall positioning calculation. Paper shows the study of the nonlinear phase filtering effects on the pseudorange estimation and demonstrates how it can be compensated with minimal hardware usage

An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance

A Comparative Study of a Low Doppler Shift in a Carrier Tracking Loop for GPS

This paper compares a carrier tracking scenario when a received Global Positioning System (GPS) signal has low Doppler frequency. It is shown that if the Numerically Controlled Oscillator (NCO) is quantized to 1 bit, the carrier tracking loop is unable to keep track of the incoming signal which leaves the tracking loop oscillating between the upper and lower bounds of the tracking loop bandwidth. One way of overcoming this problem is presented and compared with another existing solution, found in the literature, providing comparative results from the use of real-recorded off the air GPS L1 signals. Results show that the proposed method performs better tracking performance compared with the existing solution which it requires much less hardware complexity

Efficient Coefficient Store in Decomposed DFT/FFT Architectures for On-Board Processors

Fast Fourier Transform (FFT) and Discrete Fourier Transform (DFT) are the two very important building blocks of an On-Board Processor (OBP). Not only to enable processing in the frequency domain but also to perform demultiplexing/multiplexing tasks, transforms like the FFT and the DFT are widely in use. In this paper we will look at parallelisation of the FFT/DFT structures, which necessitates the decomposition of these transforms. The decomposition of the FFT or DFT into two or more smaller transforms may bring in extra operations in the form of twiddle multiplications. In this paper we will introduce an efficient strategy to store twiddle factors for the decomposed FFT/DFT processing blocks, where both the memory size and the number of accesses to the memory are minimized in comparison to the conventional methods. We designed a clever address generator unit and made use of a reduced memory approach and set the content of the memory accordingly, where the strategy is to decrease both the circuit area and the power dissipation in the FFT/DFT block to be used on the satellite's digital processing payload