Efficient Coefficient Store in Decomposed DFT/FFT Architectures for On-Board Processors

Abstract

Fast Fourier Transform (FFT) and Discrete Fourier Transform (DFT) are the two very important building blocks of an On-Board Processor (OBP). Not only to enable processing in the frequency domain but also to perform demultiplexing/multiplexing tasks, transforms like the FFT and the DFT are widely in use. In this paper we will look at parallelisation of the FFT/DFT structures, which necessitates the decomposition of these transforms. The decomposition of the FFT or DFT into two or more smaller transforms may bring in extra operations in the form of twiddle multiplications. In this paper we will introduce an efficient strategy to store twiddle factors for the decomposed FFT/DFT processing blocks, where both the memory size and the number of accesses to the memory are minimized in comparison to the conventional methods. We designed a clever address generator unit and made use of a reduced memory approach and set the content of the memory accordingly, where the strategy is to decrease both the circuit area and the power dissipation in the FFT/DFT block to be used on the satellite's digital processing payload