Electronic systems for intelligent particle tracking in the High Energy Physics field

This Ph.D thesis describes the development of a novel readout ASIC for hybrid pixel detector with intelligent particle tracking capabilities in High Energy Physics (HEP) application, called Macro Pixel ASIC (MPA). The concept of intelligent tracking is introduced for the upgrade of the particle tracking system of the Compact Muon Solenoid (CMS) experiment of the Large Hadron Collider (LHC) at CERN: this detector must be capable of selecting at front--end level the interesting particle and of providing them continuously to the back-end. This new functionality is required to cope with the improved performances of the LHC when, in about ten years' time, a major upgrade will lead to the High Luminosity scenario (HL-LHC). The high complexity of the digital logic for particle selection and the very low power requirement of 95% in particle selection and a data reduction from 200 Tb/s/cm2 to 1 Tb/s/cm2. A prototype, called MPA-Light, has been designed, produced and tested. According to the measurements, the prototype respects all the specications. The same device has been used for multi-chip assembly with a pixelated sensor. The assembly characterization with radioactive sources conrms the result obtained on the bare chip

Clonal tracking of Glioma progression

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Pix-ESL: a SystemC framework for architectural modelling of readout systems in HEP

The high cost of prototyping at advanced technology nodes, as well as the complexity of future detectors, necessitate the use of a system design technique widely used in industry: design space exploration through high-level architecture studies to establish precise and optimal requirements. This work presents Pix-ESL: a programmable SystemC framework for simulating the readout chain from the front-end chips to the detector back-end. The model is transaction accurate, comprises an event generator and connects with real-world physics events, and provides metrics such as readout efficiency, latency, and average queue occupancy. This contribution outlines the framework's structure as well as a case study based on Velopix2

Readout architecture for the Pixel-Strip module of the CMS Outer Tracker Phase-2 upgrade

The Outer Tracker upgrade of the Compact Muon Solenoid (CMS) experiment at CERN introduces new challenges for the front-end readout electronics. In particular, the capability of identifying particles with high transverse momentum using modules with double sensor layers requires high speed real time interconnects between readout ASICs. The Pixel-Strip module combines a pixelated silicon layer with a silicon-strip layer. Consequently, it needs two different readout ASICs, namely the Short Strip ASIC (SSA) for the strip sensor and the Macro Pixel ASIC (MPA) for the pixelated sensor. The architecture proposed in this paper allows for a total data flow between readout ASICs of $\sim$100\,Gbps and reduces the output data flow from 1.3\,Tbps to 30\,Gbps per module while limiting the total power density to below 100\,mW/cm$^2$. In addition a system-level simulation framework of all the front-end readout ASICs is developed in order to verify the data processing algorithm and the hardware implementation allowing multichip verification with performance evaluation. Finally, power consumption and efficiency performance are estimated and reported for the described readout architecture

System Level simulation framework for the ASICs development of a novel particle physics detector

The simulation of the passage of particles through matter using Monte Carlo methods is broadly used in the development of particle detectors for high energy physics experiments. To develop the readout electronics for the Compact Muon Solenoid (CMS) experiment at CERN, and to assist the design of the on-detector ASICs, a simulation framework was build capable to link the physics Monte Carlo simulations platforms with an industry standard EDA simulation tools. This contribution focuses on the implementation of the simulation framework based on the System Verilog language and the Universal Verification Methodology (UVM). The simulation results that guided the development of the ASICs and the choice of the final architecture are presented

Design and simulation of a 65 nm Macro-Pixel Readout ASIC (MPA) for the Pixel-Strip (PS) module of the CMS Outer Tracker detector at the HL-LHC

The MPA is the pixel readout ASIC for the hybrid Pixel-Strip module of the Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It employs a novel technique for identifying high transverse momentum particles and provides this information at 40 $MHz$ rate to the L1-trigger system. The chip also comprises a binary pipeline buffer for the L1-trigger latency, and a data path to support the readout of full events with a maximum trigger rate of 1 $MHz$ and a latency of 12.8 $\mu s$. The design and implementation in a 65 $nm$ CMOS technology of the first prototype ASIC that integrates all functionalities for system level operation with a power density lower than 90 $mW/cm^2$ are presented in this contribution

Effects of axial force variation in the seismic response of bridges isolated with friction pendulum systems

The effects of the axial load variations on the seismic response of bridges isolated with friction pendulum systems (FPS) are investigated. A series of parametric time history non-linear analyses are performed for different bridge configurations, defined after an extensive investigation on typical existing cases. The influence of both horizontal and vertical components of the ground motion is considered. The behaviour of the pier- isolator-deck system is predicted using two analytical models characterised by hysteretic loops sensitive or insensitive to axial force variations, in order to compare the different responses. Level of axial force, maximum displacements and induced bending moment are investigated, as well as shear and torsion demand, caused by different shear actions acting on the isolator devices. A comparison between demand and resistance capacity of the bridge piers is performed, in order to investigate possible non-conservative approaches in the current design methods and to raise controversial issues on the subject