Noise modeling using look-up tables and DC measurements for cryogenic applications

International audienceThere is today a lack of mature transistor-level compact models for the simulation of integrated circuits at cryogenic temperatures. This is particularly the case for the simulation of the noise behavior which is critical for most applications. In this paper, we aim at an efficient prediction of the white noise behavior of basic amplifying stages working at RF frequencies and cryogenic temperatures. For this, we propose the use of DC measurements that are incorporated in a Look-Up Table (LUT) and fed to a mathematical noise model. We illustrate the approach for the case of a transistor in common source configuration. The results of circuit simulation of the noise parameters in the standard temperature range are very close to the estimation of the same parameters using the LUT with just DC measurements. The approach can be readily extended to the analysis of circuits with multiple components. Next, the LUT approach is used for estimating the noise parameters at cryogenic conditions, considering DC measurements that have been carried out at these temperatures. The paper illustrates the feasibility of carrying out a cryogenic design using a LUT-based approach while accurate compact models are not yet available

Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration

International audienceRecord RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (&lt;500&deg;C) needed for 3D Sequential Integration (3DSI). f T =180GHz &amp; f MAX =240GHz are reported at V DD =0.9V; which is actually very similar to performance of reference Si MOSfets processed with a Hot Thermal Budget (HTB) (Fig. 15). This excellent result was possible thanks to a careful optimization of the LTB process after an advanced characterization and modeling of key technological parameters such as mobility, Gate-Capacitance and Gate resistance</p

Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration

International audienceRecord RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (&lt;500&deg;C) needed for 3D Sequential Integration (3DSI). f T =180GHz &amp; f MAX =240GHz are reported at V DD =0.9V; which is actually very similar to performance of reference Si MOSfets processed with a Hot Thermal Budget (HTB) (Fig. 15). This excellent result was possible thanks to a careful optimization of the LTB process after an advanced characterization and modeling of key technological parameters such as mobility, Gate-Capacitance and Gate resistance</p

Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration

International audienceWe present, for the first time, a new CV based technique to extract the Active Dopant Profile under the spacer in thin film FDSOI devices (CV-AJP). The methodology is successfully applied to FDSOI devices fabricated at 500&deg;C for 3D sequential integration. It shows that the ION/ IOFF trade-off relies mainly on the chemical dopant introduction below the offset spacer, as the activation level obtained with thermal activation is found to be high enough. The LT device demonstrated in this work, already outperforms the literature. The active profile extraction also allows to draw guidelines for further device performance improvement: using a scaled SiCO spacer (5,5nm) allows to circumvent the negligible dopant diffusion at 500&deg;C without dynamic performance penalty due to its low-k dielectric value.</p