Transplantation of Specific Human Astrocytes Promotes Functional Recovery after Spinal Cord Injury

Repairing trauma to the central nervous system by replacement of glial support cells is an increasingly attractive therapeutic strategy. We have focused on the less-studied replacement of astrocytes, the major support cell in the central nervous system, by generating astrocytes from embryonic human glial precursor cells using two different astrocyte differentiation inducing factors. The resulting astrocytes differed in expression of multiple proteins thought to either promote or inhibit central nervous system homeostasis and regeneration. When transplanted into acute transection injuries of the adult rat spinal cord, astrocytes generated by exposing human glial precursor cells to bone morphogenetic protein promoted significant recovery of volitional foot placement, axonal growth and notably robust increases in neuronal survival in multiple spinal cord laminae. In marked contrast, human glial precursor cells and astrocytes generated from these cells by exposure to ciliary neurotrophic factor both failed to promote significant behavioral recovery or similarly robust neuronal survival and support of axon growth at sites of injury. Our studies thus demonstrate functional differences between human astrocyte populations and suggest that pre-differentiation of precursor cells into a specific astrocyte subtype is required to optimize astrocyte replacement therapies. To our knowledge, this study is the first to show functional differences in ability to promote repair of the injured adult central nervous system between two distinct subtypes of human astrocytes derived from a common fetal glial precursor population. These findings are consistent with our previous studies of transplanting specific subtypes of rodent glial precursor derived astrocytes into sites of spinal cord injury, and indicate a remarkable conservation from rat to human of functional differences between astrocyte subtypes. In addition, our studies provide a specific population of human astrocytes that appears to be particularly suitable for further development towards clinical application in treating the traumatically injured or diseased human central nervous system

A Lego Mindstorms NXT experiment for Model Predictive Control education

This paper presents an educational framework based on the Lego Mindstorms NXT robotic platform used to outline both the theoretical and practical aspects of the Model Predictive Control theory. The case of a two-wheeled inverted pendulum is considered as at-size scenario. For such a system, starting from its mathematical modeling, an established design methodology is presented aiming to outline step-by-step the predictive controller implementation on a low-power architecture. The effectiveness of this multidisciplinary approach is illustrated along this presentation and demonstrated with experimental results

High level synthesis of Smith-Waterman dataflow implementations

The paper presents the results of design explorations for the implementation of the Smith-Waterman (S-W) algorithm executing DNA and protein sequences alignment. Both design explorations studies and the corresponding FPGA implementations are obtained by writing a dynamic dataflow program implementing the algorithm and by direct high-level synthesis (HLS) to FPGA HDL. The main feature of the obtained implementation is a low-latency, pipelinable multistage processing element (PE), providing a substantial decrease in the resource utilization and an increase in the computation throughput when compared to state of the art solutions. The implementation solution is also fully scalable and can be efficiently reconfigured according to the DNA sequence sizes and to system performance requirements. The FPGA design presented in the paper can efficiently scale up to 250 MHz obtaining 14746 Alignments/s using a single S-W core with 4 PEs, and up to 31.8 Mega-Alignments/min using 36 S-W cores on the same FPGA for sequences of 160×100 nucleotides

Trace-based manycore partitioning of stream-processing applications

Application performance on these processor array platforms is highly sensitive to how functionality is physically placed on the device, as this choice crucially determines communication latencies and congestion patterns of the on-chip inter-core communication. The problem of identifying the best, or just a good enough, partitioning and placement does not, in general, admit to an analytic solution, and its combinatorial nature makes solving it by pure experimentation impractical. This paper presents an approach that maps stream programs onto processor arrays using trace analysis as a technique for evaluating candidate solutions and for suggesting alternatives

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case

Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platforms require to address several issues. The higher is the system complexity, the more error prone and time consuming is the entire design flow. Moreover, system configuration along with resource management and mapping are challenging, especially when runtime adaptivity is required. In order to address these issues, the Reconfigurable Video Coding Group within the MPEG group has developed the MPEG RMC standards ISO/IEC 23001-4 and 23002-4, based on the dataflow Model of Computation. In this paper, we propose an integrated design flow, leveraging on Xronos, TURNUS, and the Multi-Dataflow Composer tool, capable of automatic synthesis and mapping of reconfigurable systems. In particular, an RVC MPEG-4 SP decoder and the RVC Intra MPEG-4 SP decoder have been implemented on the same coarse-grained reconfigurable platform, targeting a Xilinx Virtex 5 330 FPGA board. Results confirmed the potentiality of the approach, capable of completely preserving the single decoders functionality and of providing, in addition, considerable power/area benefits with respect to the parallel implementation of the considered decoders on the same platform

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case

Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platforms require to address several issues. The higher is the system complexity, the more error prone and time consuming is the entire design flow. Moreover, system configuration along with resource management and mapping are challenging, especially when runtime adaptivity is required. In order to address these issues, the Reconfigurable Video Coding Group within the MPEG group has developed the MPEG RMC standards ISO/IEC 23001-4 and 23002-4, based on the dataflow Model of Computation. In this paper, we propose an integrated design flow, leveraging on Xronos, TURNUS, and the Multi-Dataflow Composer tool, capable of automatic synthesis and mapping of reconfigurable systems. In particular, an RVC MPEG-4 SP decoder and the RVC Intra MPEG-4 SP decoder have been implemented on the same coarse-grained reconfigurable platform, targeting a Xilinx Virtex 5 330 FPGA board. Results confirmed the potentiality of the approach, capable of completely preserving the single decoders functionality and of providing, in addition, considerable power/area benefits with respect to the parallel implementation of the considered decoders on the same platform. © 2014 IEEE

TURNUS: an open-source design space exploration framework for dynamic stream programs

Although the research on the design of heterogeneous concurrent systems has a long and rich history, a unified design methodology and tool support have not emerged so far. Therefore, the creation of such systems remains a difficult, time-consuming and error-prone process. The absence of principled support for system evaluation and optimization at high level of abstraction makes the quality of the resulting implementation strongly dependent on the experience or individual preferences of the designer. In this work we are presenting TURNUS, a unified dataflow design space exploration framework for heterogeneous parallel systems. This open source framework represents a decade of research on high-level modelling and simulation methods and tools for system level performance estimation and optimization. Last year we presented heuristic algorithms that were focused on the results of exploration in terms of algorithmic optimization, rapid performance estimation, application throughput, buffer size dimensioning and power optimization. This year we are presenting the novelties that have been introduced in TURNUS such as clock gating, pipelining optimization, kernel splitting algorithms, advanced partitioning algorithms and scheduling optimization based on model predictive control techniques