A Spatiotemporal Pattern Detector

A spatiotemporal pattern detector design is presented which can identify three fundamental spatiotemporal patterns consisting of two spikes (from different neurons or from the same neuron). These fundamental cases provide the building blocks for construction of more complicated arbitrary spatiotemporal patterns. The overall design consists of three primary subcircuits, and the operation of each is described. The detection of the three cases of spatiotemporal patterns, and the detection of a more complicated pattern by a network of Spatiotemporal Pattern Detectors, is then demonstrated through simulation using the Cadence Virtuoso platform

Electrical Characteristics of Nanocrystalline Silicon Resistive Memory Devices

Resistive memory devices have been studied and fabricated using a wide variety of materials including chalcogenides [1], metal oxides [2], and hydrogenated amorphous silicon (a-Si:H) [3]. The most promising materials seem to be amorphous in nature, with the properties of the atomic lattices being conducive to the physical mechanisms that underlie the subsequent resistive switching. The devices are also finding applications beyond high-density digital memory, such as for electronic synapses in neuromorphic systems [4], [5]. However, a different set of properties is required in the latter case compared to devices that must only store binary values. In addition, it is well known that biological synapses are extremely unreliable and noisy, and yet the brain is still able to perform high-level cognitive functions [6]-[8]. This work uses pulse-based electrical characterization techniques to demonstrate the stochastic nature of resistive switching in nanocrystalline silicon (nc-Si) Conductive Bridge Resistive Memory (CBRAM) Devices. We chose nc-Si active layers so these devices could potentially be co-fabricated in the same process as nc-Si TFTs [9]-[11]. Our subsequent findings indicate the device properties may be particularly useful for some non-von Neumann computing paradigms. Though much research has been done using a-Si:H, results from nc-Si CBRAM devices have not been published. In this study, we showed that the switching of the device depends on the history of current passing though it, and not only the voltage applied. Further, the resistance switching in the devices is stochastic, making them ideal candidates for a biologically realistic synapse

Logic Gates and Ring Oscillators Based on Ambipolar Nanocrystalline-Silicon TFTs

Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) are well suited for circuit applications that require moderate device performance and low-temperature CMOS-compatible processing below 250°C. Basic logic gate circuits fabricated using ambipolar nc-Si TFTs alone are presented and shown to operate with correct outputs at frequencies of up to 100 kHz. Ring oscillators consisting of nc-Si TFT-based inverters are also shown to operate at above 20 kHz with a supply voltage of 5 V, corresponding to a propagation delay of 5 V for several hours

Work in Progress: Mastery-Based Grading in an Introduction to Circuits Class

Circuits is often the first required course in an electrical engineering curriculum that demands application of multiple concepts from prerequisite math and physics courses. This integration of knowledge can be a challenge for many students. Effective teaching methods can enhance the overall learning experience, increase program retention, and improve student understanding of foundational topics in electrical engineering. This paper outlines a mastery-based grading structure implemented in a sophomore-level circuits class. The focus is placed at this level because the course is a critical prerequisite for many other courses in the electrical and computer engineering (ECE) curriculum. The knowledge that students are expected to gain in circuits is paramount to successful completion of their degree. However, faculty often observe that many students pass circuits without being able to consistently apply many of the fundamental concepts therefore causing them to struggle through subsequent courses. The overall goal of this mastery-based grading scheme is to create a more positive student learning experience that also translates to improved long-term performance. It also helps to alleviate some level of test anxiety and the stress students feel in a fast-paced, rigorous course such as circuits

A CMOS Synapse Design Implementing Tunable Asymmetric Spike Timing-Dependent Plasticity

A CMOS synapse design is presented which can perform tunable asymmetric spike timing-dependent learning in asynchronous spiking neural networks. The overall design consists of three primary subcircuit blocks, and the operation of each is described. Pair-based Spike Timing-Dependent Plasticity (STDP) of the entire synapse is then demonstrated through simulation using the Cadence Virtuoso platform. Tuning of the STDP curve learning window and rate of synaptic weight change is possible using various control parameters. With appropriate settings, it is shown the resulting learning rule closely matches that observed in biological systems

Spatio-Temporal Pattern Recognition in Neural Circuits with Memory-Transistor-Driven Memristive Synapses

Spiking neural circuits have been designed in which the memristive synapses exhibit spike timing-dependent plasticity (STDP). STDP is a learning mechanism where synaptic weight (the strength of the connection between two neurons) depends on the timing of pre-and post-synaptic action potentials. A known capability of networks with STDP is detection of simultaneously recurring patterns within the population of afferent neurons. This work uses SPICE (simulation program with integrated circuit emphasis) to demonstrate the spatio-temporal pattern recognition (STPR) effect in networks with 25 afferent neurons. The neuron circuits are the leaky integrate-and-fire (I&F) type and implemented using extensively validated ambipolar nano-crystalline silicon (nc-Si) thin-film transistors (TFT) models. Ideal memristor synapses are driven by a nanoparticle memory thin-film transistor (np-TFT) with a short retention time attached to each neuron circuit output. This device serves to temporally modulate the conductance path from post-synaptic neurons, providing rate-based and timing-dependent learning. With this configuration, the use of a crossbar structures would also be possible, providing dense synaptic connections and potentially reduced energy consumption

Signal-to-Noise Ratio Enhancement Using Graphene-Based Passive Microelectrode Arrays

This work is aimed toward the goal of investigating the influence of different materials on the signal-to-noise ratio (SNR) of passive neural microelectrode arrays (MEAs). Noise reduction is one factor that can substantially improve neural interface performance. The MEAs are fabricated using gold, indium tin oxide (ITO), and chemical vapor deposited (CVD) graphene. 3D-printed Nylon reservoirs are then adhered to the glass substrates with identical MEA patterns. Reservoirs are filled equally with a fluid that is commonly used for neuronal cell culture. Signal is applied to glass micropipettes immersed in the solution, and response is measured on an oscilloscope from a microprobe placed on the contact pad external to the reservoir. The time domain response signal is transformed into a frequency spectrum, and SNR is calculated from the ratio of power spectral density of the signal to the power spectral density of baseline noise at the frequency of the applied signal. We observed as the magnitude or the frequency of the input voltage signal gets larger, graphene-based MEAs increase the signal-to-noise ratio significantly compared to MEAs made of ITO and gold. This result indicates that graphene provides a better interface with the electrolyte solution and could lead to better performance in neural hybrid systems for in vitro investigations of neural processes

Characterization of Inkjet-Printed Features for Electronic Applications

Printed electronics, a form of additive manufacturing, is a growing field because it uses less energy, fewer raw materials, and produces less waste than traditional electronics manufacturing. In this study, electronic features were inkjet printed using a Fujifilm Dimatix DMP-2831 printer. Silver nanoink from Novacentrix and metallic carbon nanotube ink from NanoIntergris were the conductive materials. Shapes such as line and bridge resistors were printed on polyimide (flexible plastic) substrates. After printing, the shapes were annealed at temperatures less than 200 °C to sinter the silver and evaporate remaining solvents. After processing, all features were characterized using optical microscopy for resolution, profilometry for thickness, and electrical testing for resistivity. This study showed favorable results amongst thin lines widely spaced apart and thick bridge resistors

Characterization and Validation of CMOS Spiking Neuron Circuits

Brain-inspired chips are being designed to efficiently process complex information and accomplish tasks such as pattern recognition, object detection, and noise reduction and filtering. For this research, we are testing complementary metal-oxide-semiconductor (CMOS) devices such as transistors. We are also examining different CMOS circuits including inverters and leaky integrate-and-fire neurons using a microprobe station. The neuron circuits are expected to generate voltage pulses that mimic the action potentials of neurons found in the brain. The frequency of these pulses changes with input stimulus but pulse widths remain constant. This stimulus is directly proportional to the frequency at which spikes are generated and if this increase the frequency will increase too. We analyze the behavior by examining the generated voltage versus time and frequency versus current graphs. Extracted data is then compared to simulation as well as biological measurements obtained from the literature to demonstrate the effectiveness of the chip

Electrically Controlling the Environmental Interactions of Neurons Cultured on Graphene

In neural interfaces, a major challenge is finding an electronic material that will be accepted by the human body. Currently, electrode arrays are often made from silicon, but graphene seems to be a better material for humans due to its biocompatibility and flexibility. However, it is unknown how neural cells react to being electrically stimulated on graphene. For this work, we will observe the interactions between graphene electrodes and cultured neural stem cells using a probe station specially designed for electrophysiology. The cells are kept in a salt solution contained in a 3D printed reservoir. This is mounted on top of a graphene sample and is attached to a fluidic system consisting of two pump controllers that refresh the solution at a small rate, thus keeping the cells alive for several hours. This also allows us to introduce different salt concentrations and/or chemicals that modify the cellular environment, and thus the interactions with the graphene. The cells must be kept at a temperature of 37°C, which is achieved by using a heating pad attached to a chuck. Currently, we have the pump controllers working and have been able to control them using a computer