GaN-on-silicon transistors with reduced current collapse and improved blocking voltage by means of local substrate removal

International audienceWe report on the demonstration of low trapping effects above 1200 V of GaN-on-silicon transistors using a local substrate removal (LSR) followed by a thick backside ultra-wide-bandgap AlN deposition. Substrate ramp measurements show reduced hysteresis up to 3000 V. It has been found that the LSR approach not only enable to extend the operation voltage capabilities of GaN-on-Silicon HEMTs with low on-resistance but also allow to reduce trapping effects directly affecting their dynamic behavior. This work points out that a large part of the electron trapping under high bias occurs at the AlN nucleation layer and Si substrate interface

Reliability and failure analysis in power GaN-HEMTs: An overview

ower GaN transistors have recently demonstrated to be excellent devices for application in power electronics. The high breakdown field and the superior mobility of the 2-dimensional electron gas allow to fabricate transistors with low resistive and switching losses, that permit to increase the efficiency of switching mode power converters beyond 99 %. GaN-based transistors are currently supposed to be adopted in KW-range power converters; 650 V transistors are already available on the market, and 1200 V devices are currently under development. During operation, GaN power transistors can reach critical conditions, especially in the off-state (with a high VDS, in excess of 650 V), during hard-switching (where high current and voltage can be simultaneously present), and for high positive gate voltages (in the case of normally-off devices). This paper reports our most recent results on the gradual and catastrophic degradation of GaN-based power HEMTs. We present the results of three different case studies, on: (i) the time-dependent breakdown of power HEMTs submitted to high off-state stress; (ii) the degradation of HEMTs with p-GaN gate submitted to high gate stress; (iii) the hot electron effects in GaN-MISHEMTs submitted to high-Temperature source current stres

Degradation of GaN-HEMTs with p-GaN Gate: Dependence on temperature and on geometry

This paper investigates the time-dependent degradation of normally-off transistors with p-GaN gate submitted to constant voltage stress. Based on combined dc characterization and temperature-dependent analysis, we study the dependence of time-To-failure on stress temperature and device geometry. The results of this analysis indicate that: (i) normally-off transistors with p-GaN gate have a good stability, reaching a 20 years lifetime with a 7.2 V gate bias; (ii) at higher stress voltages, a time-dependent failure is observed. Time-To-failure (TTF) depends exponentially on stress voltage, while failure is ascribed to a localized breakdown process that takes place in the p-GaN/AlGaN stack; (iii) TTF scales with device area only if the area is changed by increasing the gate width (and not if area is increased by modifying gate length). This result suggests that degradation occurs mostly in proximity of the gate edge, rather than at the center of the gate. (iv) finally, stress tests carried out at different temperature levels indicate that TTF is dependent on temperature, with activation energy of 0.48-0.50 eV