Continuous Inverse Class-F GaN Power Amplifier with 70% Efficiency over 1.4-2 GHz Bandwidth

This work presents the design and experimental characterization of a wideband continuous inverse class-F power amplifier, covering several bands in the 5G FR1 frequency range, and thus suitable for base station applications. The design spaces of the class-F and inverse class-F in terms of input and output terminations are reviewed and compared, and the design choices relative to an implementation using a packaged device are described. Measurements show a saturated output power of 40 dBm, with corresponding efficiency and gain higher than 70% and 13 dB, respectively, over 1.4-2 GHz. The performance is well in line with the state of the art and is accurately predicted by simulations, proving the effectiveness of the design strategy

A Simple Method to Identify Parametric Oscillations in Power Amplifiers Using Harmonic Balance Solvers

A qualitative method to verify the presence of parametric oscillations at f_0/2 in power amplifiers (PAs) is presented and validated. It relies on the simultaneous application of fundamental and subharmonic tones to trigger possible parametric oscillations and can be implemented in any commercial harmonic balance solver without requiring any external software that may be expensive or however not available to the designer. Wide applicability is guaranteed by the fact that this method does not require access to any internal node of the circuit. In fact, the amplifier is handled as a black-box where only the input and output ports are accessible. The stability check is first demonstrated on a simplified case study and then validated on a real K-band integrated PA, where it correctly reproduces with simulations the parametric oscillations observed by measurements. On the redesigned amplifier, the proposed test predicted the absence of oscillations, which has been confirmed by the experimental characterization

Optimisation of a Doherty power amplifier based on dual-input characterisation

The success of the Doherty architecture compared to other efficiency enhancement techniques derives mainly from its simple design and full-RF nature, not requiring complex digital signal processing to achieve high back-off efficiency. In this work we propose a design strategy for the optimisation of a Doherty power amplifier to mitigate the typical practical issues of this architecture related to inaccuracy of the non-linear model and of the manufacturing. The approach is based on the experimental characterisation of a dual-input Doherty prototype without input section. This test structure is obtained from a single-input Doherty amplifier, designed only through non-linear simulations, by removing the input section and allowing for separate control of the two RF inputs. From the collected data, approximated functions for the phase shift and power splitting versus frequency are identified to be realizable in hardware with RF networks. Compared to the reference single-input Doherty stage, a significantly improved behavior is registered in terms of output power (up to 2.7 dB), efficiency at saturation and back-off (30 % and 15 % respectively) and power gain (2 dB)

A Novel Stacked Cell Layout for High Frequency Power Applications

This letter presents an innovative stacked cell, where the common source device is split in two smaller devices leading to a more compact and symmetric structure, with almost negligible parasitics associated to the transistors connection. This novel configuration is rigorously compared, for the first time, with the two classical approaches commonly adopted to physically connect the two devices. The three different layouts are fabricated in Gallium Nitride technology for high frequency power applications, and experimentally compared by means of an extensive measurement campaign performed on several loads and in different bias conditions, ranging from class AB to C. The proposed novel configuration outperforms the other two in all conditions, thanks to the advantages of adopting two smaller devices with reduced parasitics, higher gain and higher power density. These features are common to different technologies, thus making the novel topology widely applicable for the design of high frequency stacked cells

Design of a wideband doherty power amplifier with high efficiency for 5g application

This paper discusses the design of a wideband class AB-C Doherty power amplifier suitable for 5G applications. Theoretical analysis of the output matching network is presented, focusing on the impact of the non-ideally infinite output impedance of the auxiliary amplifier in back off, due to the device’s parasitic elements. By properly accounting for this effect, the designed output matching network was able to follow the desired impedance trajectories across the 2.8 GHz to 3.6 GHz range (fractional bandwidth = 25%), with a good trade-off between efficiency and bandwidth. The Doherty power amplifier was designed with two 10 W packaged GaN HEMTs. The measurement results showed that it provided 43 dBm to 44.2 dBm saturated output power and 8 dB to 13.5 dB linear power gain over the entire band. The achieved drain efficiency was between 62% and 76.5% at saturation and between 44% and 56% at 6 dB of output power back-off

A 5-W GaN Doherty Amplifier for Ka-Band Satellite Downlink With 4-GHz Bandwidth and 17-dB NPR

This letter presents the design and experimental characterization of a GaN-Si monolithic Doherty power amplifier (PA) for the Ka-band satellite downlink. The fabricated amplifier favorably compares with the current state of the art, achieving from 16.3 to 20.3 GHz (4 GHz, 22% relative bandwidth), a record band to date, 36.6-37.7-dBm output power, 23%-31% power-added efficiency, 18-22-dB gain at saturation, and around 20% power-added efficiency at 6-dB output back-off. At 18.8 GHz, the amplifier shows a noise-to-power ratio higher than 17 dB at all power levels, making it suitable for satellite applications where additional linearization is usually unfeasible

A GaN MMIC stacked doherty power amplifier for space applications

This paper presents the design and the experimental results of a Monolithic Microwave Integrated Circuit Power Am-plifier in which the transistor-stacking approach is used within the Doherty architecture in order to maximize the achievable performance. In particular, the Stacked cell is realized by dividing the common source transistor in two smaller devices leading to a very compact and symmetric structure, whereas the Doherty approach is exploited to fulfil high efficiency at back-off. The chip has been manufactured on a 100 nm gate length GaN high electron mobility technology, growth on Silicon substrate and targeting the satellite downlink Ka-band. The two-stage amplifier was designed to meet the power requirements while satisfying the thermal constraints for use in space applications. In the frequency range from 17.3 GHz to 20.3 GHz, measurement results have shown a linear gain of about 25 dB with a peak power of 38dBm and a power added efficiency larger than 35%