Red mark syndrome: Is the aquaculture water microbiome a keystone for understanding the disease aetiology?

Aquaculture significantly contributes to the growing demand for food worldwide. However, diseases associated with intensive aquaculture conditions, especially the skin related syndromes, may have significant implications on fish health and industry. In farmed rainbow trout, red mark syndrome (RMS), which consists of multiple skin lesions, currently lacks recognized aetiological agents, and increased efforts are needed to elucidate the onset of these conditions. Most of the past studies were focused on analyzing skin lesions, but no study focused on water, a medium constantly interacting with fish. Indeed, water tanks are environmental niches colonized by microbial communities, which may be implicated in the onset of the disease. Here, we present the results of water and sediment microbiome analyses performed in an RMS-affected aquaculture facility, bringing new knowledge about the environmental microbiomes harbored under these conditions. On the whole, no significant differences in the bacterial community structure were reported in RMS-affected tanks compared to the RMS-free ones. However, we highlighted significant differences in microbiome composition when analyzing different samples source (i.e., water and sediments). Looking at the finer scale, we measured significant changes in the relative abundances of specific taxa in RMS-affected tanks, especially when analyzing water samples. Our results provide worthwhile insight into a mostly uncharacterized ecological scenario, aiding future studies on the aquaculture built environment for disease prevention and monitoring

Design of Hardened Embedded Systems on Multi-FPGA Platforms

The aim of this article is the definition of a reliability-aware methodology for the design of embedded systems on multi-FPGA platforms. The designed system must be able to detect the occurrence of faults globally and autonomously, in order to recover or to mitigate their effects. Two categories of faults are identified, based on their impact on the device elements; (i) recoverable faults, transient problems that can be fixed without causing a lasting effect namely and (ii) nonrecoverable faults, those that cause a permanent problem, making the portion of the fabric unusable. While some aspects can be taken from previous solutions available in literature, several open issues exist. In fact, no complete design methodology handling all the peculiar issues of the considered scenario has been proposed yet, a gap we aim at filling with our work. The final system exposes reliability properties and increases its overall lifetime and availability

Identifying aging-aware representative paths in processors

Conference of 21st IEEE International On-Line Testing Symposium, IOLTS 2015 ; Conference Date: 6 July 2015 Through 8 July 2015; Conference Code:117277International audienceThis paper proposes a method to select a set of paths representative of the behavior of a processor under NBTI conditions. The selected paths are the ones that are expected to fail first due to aging for any executed application

Fine-grain analysis of the parameters involved in aging of digital circuits

Conference of 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016 ; Conference Date: 4 July 2016 Through 6 July 2016; Conference Code:124500International audienceIntegrated circuits' aging is recognized as a key reliability bottleneck. Its estimation at design time is mandatory to define the lifetime of the circuit and its monitoring during the circuit's operation is necessary to guarantee high performances and avoid timing failures. Various parameters are involved in the process of aging. The knowledge of their impact can help the designer in optimizing the estimation at design time or selecting which parameters are most critical to monitor. This paper presents a fine-grain analysis of the parameters involved in the degradation of digital circuits

When processors get old: Evaluation of BTI and HCI effects on performance and reliability

Conference of 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013 ; Conference Date: 8 July 2013 Through 10 July 2013; Conference Code:99890International audienceThis paper investigates the problem of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) on processors. We propose a performance- and reliability-aware methodology that evaluates the effects of these degradation mechanisms at design time. The performed analysis estimates the effects produced by the execution of applications, representing typical or worst case scenarios, or single instructions. As shown by the experimental results, our framework allows to estimate the performance degradation and to identify the areas of memory most subject to faults, with the objective of optimizing the system design and defining on-line strategies

Optimizing Service Selection and Allocation in Situational Computing Applications

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6205728&contentType=Early+Access+Articles&searchWithin%3Dp_Authors%3A.QT.Ardagna%2C+D..QT.%26searchField%3DSearch_All This paper describes a novel model for the service selection problem of workflow-based applications in the context of self-managing situated computing. In such systems, the execution environment includes different types of devices, from remote servers to personal notebooks, smartphones, and wireless sensors, which build an infrastructure that can dynamically change both its physical and logical architecture at run-time. We assume that worflows are defined abstractly; i.e., they invoke abstract services whose concrete counterparts can be selected dynamically. We also assume that concrete service implementations may possibly migrate on the nodes of the infrastructure. The selection problem we address is framed as an optimization problem of the quality of service, which evaluates at run-time the optimal binding to concrete services as well as the trade-off between the remote execution of software fragments and their dynamic deployment on local nodes of the computational environment. The final deployment takes into account quality of service constraints, the capabilities of the physical devices involved, including their performance and energy consumption, and the characteristics of the networking links connecting them. <br/

Adaptive genetic algorithm for dynamically reconfigurable modules allocation

This paper aims at defining an adaptive genetic algorithm tailored for the allocation of dynamically reconfigurable modules. This algorithm can be tuned at run-time with a set of parameters to best characterize different architectural scenarios (i.e., single device or multi-FPGAs characterized by several kinds of communication infrastructures) and to adapt the performance of the algorithm itself to the scenario in which it has to operate. The proposed approach has been validated with a large set of meaningful combinations of parameters (i.e. changing the mutation or the crossover probability), in order to demonstrate the possibility of performing either a fast or an accurate allocation phase

An integrated flow for the design of hardened circuits on SRAM-based FPGAs

Abstract—This paper presents an enhanced design flow for the implementation of hardened systems on SRAM-based FPGAs, able to cope with the occurrence of Single Event Upsets (SEUs). The framework integrates three strategies independently designed to tackle the problem of SEUs; first a systematic methodology is used to harden the circuit exploiting an enhanced TMRbased technique, coupled with partial dynamic reconfiguration. Then, a robustness analysis is performed to identify possible TMR failures, eventually solved by a specific local re-design of the critical portions of the implementation. We present the overall flow and the benefits of the solution, experimentally evaluated on a realistic circuit