Towards accurate and precise T1 and extracellular volume mapping in the myocardium: a guide to current pitfalls and their solutions

Mapping of the longitudinal relaxation time (T1) and extracellular volume (ECV) offers a means of identifying pathological changes in myocardial tissue, including diffuse changes that may be invisible to existing T1-weighted methods. This technique has recently shown strong clinical utility for pathologies such as Anderson- Fabry disease and amyloidosis and has generated clinical interest as a possible means of detecting small changes in diffuse fibrosis; however, scatter in T1 and ECV estimates offers challenges for detecting these changes, and bias limits comparisons between sites and vendors. There are several technical and physiological pitfalls that influence the accuracy (bias) and precision (repeatability) of T1 and ECV mapping methods. The goal of this review is to describe the most significant of these, and detail current solutions, in order to aid scientists and clinicians to maximise the utility of T1 mapping in their clinical or research setting. A detailed summary of technical and physiological factors, issues relating to contrast agents, and specific disease-related issues is provided, along with some considerations on the future directions of the field. Towards accurate and precise T1 and extracellular volume mapping in the myocardium: a guide to current pitfalls and their solutions. Available from: https://www.researchgate.net/publication/317548806_Towards_accurate_and_precise_T1_and_extracellular_volume_mapping_in_the_myocardium_a_guide_to_current_pitfalls_and_their_solutions [accessed Jun 13, 2017]

The impact of surgical delay on resectability of colorectal cancer: An international prospective cohort study

AIM: The SARS-CoV-2 pandemic has provided a unique opportunity to explore the impact of surgical delays on cancer resectability. This study aimed to compare resectability for colorectal cancer patients undergoing delayed versus non-delayed surgery. METHODS: This was an international prospective cohort study of consecutive colorectal cancer patients with a decision for curative surgery (January-April 2020). Surgical delay was defined as an operation taking place more than 4 weeks after treatment decision, in a patient who did not receive neoadjuvant therapy. A subgroup analysis explored the effects of delay in elective patients only. The impact of longer delays was explored in a sensitivity analysis. The primary outcome was complete resection, defined as curative resection with an R0 margin. RESULTS: Overall, 5453 patients from 304 hospitals in 47 countries were included, of whom 6.6% (358/5453) did not receive their planned operation. Of the 4304 operated patients without neoadjuvant therapy, 40.5% (1744/4304) were delayed beyond 4 weeks. Delayed patients were more likely to be older, men, more comorbid, have higher body mass index and have rectal cancer and early stage disease. Delayed patients had higher unadjusted rates of complete resection (93.7% vs. 91.9%, P = 0.032) and lower rates of emergency surgery (4.5% vs. 22.5%, P < 0.001). After adjustment, delay was not associated with a lower rate of complete resection (OR 1.18, 95% CI 0.90-1.55, P = 0.224), which was consistent in elective patients only (OR 0.94, 95% CI 0.69-1.27, P = 0.672). Longer delays were not associated with poorer outcomes. CONCLUSION: One in 15 colorectal cancer patients did not receive their planned operation during the first wave of COVID-19. Surgical delay did not appear to compromise resectability, raising the hypothesis that any reduction in long-term survival attributable to delays is likely to be due to micro-metastatic disease

The Chip is Ready. Am I done? On-chip Verification using Assertion Processors

White-box verification is a technique that reduces observability problems by locating a failure during design simulation without the need to propagate the failure to the I/O pins. White-box verification in chip level designs can be implemented using assertion checkers to ensure the correct behavior of a design. With chip gate counts growing exponentially, today’s verification techniques, such as white-box, can not always ensure a bug free design. This paper proposes an assertion processor to be used with synthesized assertion checkers in released products to enable intelligent debugging of deployed designs. Extending white-box verification techniques to deployed products helps locate errors that were not found during simulation / emulation phases. We present results of the insertion of assertion checkers and an assertion processor in an 8-Bit processor and a communication core. 1

Efficient power management in real-time embedded systems

Abstract — Power consumption became a crucial problem in the development of mobile devices, especially those that are communication intensive. In these devices, it is imperative to reduce the power consumption devoted to maintaining a communication link during data transmission/reception. The application of dynamic power management methodologies has contributed to the reduction of power consumption in general purpose computer systems. However, to further reduce power consumption in communication intensive real-time embedded devices we have to consider the state of the computation and external events in addition to power management policies. In this paper we propose a model of an Extended Power State Machine (EPSM), where we adapt a Power State Machine to include the state of an embedded program in the power state machine formulation. This EPSM model is used to adapt the Quality of Service (QoS) in communication intensive devices to ensure low power consumption. In such development, a middleware layer fits in the system’s architecture, being responsible for intercepting the data communication and implementing the EPSM. Also, a software tool was developed, allowing the Middleware Code to be generated based on the State Machine. A case study demonstrates the application of the proposed model to a real situation. I