Comment on “How not to test for philosophical expertise”

Rini 2015 [Synthese 192, (2): 431-452] claims to have identified a methodological flaw that invalidates the results of two experimental studies [Schwitzgebel & Cushman (2012) Mind and Language 27, (2): 135-153; Tobia, Buckwalter & Stich (2013) Philosophical Psychology 26, (5): 629–638] demonstrating order effects in professional philosophical intuition. This conclusion is reached on the basis of unsupported empirical premises for which no evidence is given. Subsequent findings in experimental cognitive science further reveal this as unsupported speculation

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

A 10Gb/s data-dependent jitter equalizer

An equalization circuit is presented that reduces data-dependent jitter by aligning data transition deviations. This paper presents an analytic solution to data-dependent jitter and demonstrates its impact on the phase noise of the recovered clock. A data-dependent jitter equalizer is presented that compensates for impairment of the channel and lowers the phase noise of the recovered clock. The circuit is implemented in a SiGe BiCMOS process and operates at 10 Gb/s. It suppresses phase noise resulting from data-dependent jitter by 10 dB

Cancellation of crosstalk-induced jitter

A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre- or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10^sup-12 BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps

Estimating data-dependent jitter of a general LTI system from step response

We present a method for estimating data dependent jitter (DDJ) introduced by a general LTI system, based on the system's step response. A perturbation technique is used to generalize the analytical expression for DDJ. Different scales of DDJ are defined that characterize the probability distribution of jitter. In particular, we identify a dominant prior bit that signifies the well-known distribution of DDJ, the two impulse functions. We also highlight that system bandwidth is not a complete measure for predicting DDJ. We verify our generalized analytical expression of DDJ experimentally and show that estimation errors are less than 7.5%

Phase and amplitude pre-emphasis techniques for low-power serial links

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s

La maldición de los recursos: ¿Es el petróleo causa de conflicto?

Reseña de: Kaldor, Mary; Karl, Terry; Said, Yahia (eds.), Oil Wars, Pluto Press, Londres, 200

Data-dependent jitter and crosstalk-induced bounded uncorrelated jitter in copper interconnects

This paper resolves the jitter impairment of non-return-to-zero data in transmission lines. The limited bandwidth of the transmission line introduces data-dependent jitter. Crosstalk between neighbouring lines results in bounded uncorrelated jitter in the data eye. An analytical approach to representing data-dependent jitter and crosstalk-induced bounded uncorrelated jitter is presented. Comparison with jitter measurements of microstrip lines on FR4 board demonstrated accuracy to within 15% of the predictions for deterministic jitter