Impact of optical I/O on FPGA electronic routing delays

Besides the actual optical link delay the mere presence of optical interconnect also has its impact on the on-chip electrical routing delays. We quantify these delays for a real (small scale) optoelectronic FPGA prototype. Our results indicate that future designs must consider this impact to achieve optimal performance

Sense and nonsense of logic-level optical interconnect: reflections on an experiment

Centimeter-range high-density optical interconnect between chips is coming into reach with current optical interconnect technology. Many theoretical studies have identified several good reasons why to use such types of interconnect as a replacement of various layers of the traditional electronic interconnect hierarchy. However, the true feasibility and usefulness of optical interconnects can only be established by actually building and evaluating them in a real systems setting. This contribution reports on our experience in using short-range high-density optical inter-chip interconnects. It is based on the design and construction of a fully functional optoelectronic demonstrator system. We discuss the rationale for building the demonstrator in the first place, the implications of using many low-level optical interconnections in electronic systems, and the degree to which our expectations have been fulfilled by the demonstrator. The detailed description of the architecture, design and implementation of the demonstrator is not presented here, but can be found elsewhere in this issue

Ontwerp en VLSI implementatie van de instructieset van een custom grafische coprocessor. /

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