Assessing Scrubbing Techniques for Xilinx SRAM-based FPGAs in Space Applications

SRAM-based FPGAs are becoming increasingly attractive for use in space applications due to their reconfigurability and signal processing capabilities, as well as their increasing speed and capacity. Traditional SRAM-based FPGAs, however, are highly sensitive to the ionizing radiation environment in space, making them prone to radiation-induced memory upsets. In this paper, we evaluate and compare scrubbing techniques for Xilinx SRAM-based FPGAs with respect to radiation-induced single event upsets. A test framework using an exchangeable payload is developed for this purpose and run on a Xilinx Virtex-5 FPGA. We show that recent SRAM-based FPGAs can constitute a cost-efficient alternative to radiation-hardened or antifuse FPGAs for non-critical space application such as satellite instruments

Hummingbird - Tweet till elektronisk dörrskylt

Den här rapporten beskriver utvecklingen av en prototyp till ett system, Hummingbird, som låter användaren uppdatera en trådlös dörrskylt varifrån som helst, via mikrobloggtjänsten Twitter. Systemet har utvecklats som ett kandidatarbete vid Data- och IT-institutionen vid Chalmers Tekniska Högskola, Göteborg. Projektgruppen har bestått av sex teknikstuderande från Chalmers och Göteborgs Universitet. Resultatet är ett fungerande system bestående av två delar: en dörrskylt med display samt en basstation som hämtar meddelanden från Twitter. Skylten och basstationen kommunicerar via en radiolänk. Projektets huvudsakliga fokus ligger på energieffektivitet hos skylten. Även användarvänlighet och robusta kommunikationsprotokoll har prioriterats. Som en del i projektets fokus på energieffektivitet har tekniker för strömsnåla displayer, radiokommunikationsmoduler och microcontrollerplattformar undersökts och använts. Användarvänligheten ligger i skyltens trådlöshet, enkla konfigurering, samt dess fysiska dimensioner som möjliggör enkel montering på en dörr eller vägg. Slutligen ges systemet robusthet av pålitliga kommunikationsprotokoll för nätverk och radiolänk mellan basstation och skylt

Evaluating Branch Predictor Configurations for a MIPS-like Pipeline

In this report, we investigate the implementation and efficiency of different types of branch predictors. A configurable VHDL model of a branch predictor unit, composed of a branch direction predictor and a branch target buffer, has been implemented. In order to make informed hardware decisions, different branch predictor configurations are simulated using the open source SimpleScalar simulator and the MiBench benchmark suite. The target architecture is a 7-stage 32-bit MIPS-based pipeline with two instruction fetch stages

The iDEA DSP block based soft processor for FPGAs

DSP blocks in modern FPGAs can be used for a wide range of arithmetic functions, offering increased performance, while saving logic resources for other uses. They have evolved to better support a plethora of signal processing tasks, meaning that in other application domains, they may be under-utilised. The DSP48E1 primitives in new Xilinx devices support dynamic programmability, that can help extend their usefulness; the specific function of a DSP block can be modified on a cycle by cycle basis. However, the standard synthesis flow does not leverage this flexibility in the vast majority of cases. The lean DSP Extension Architecture (iDEA) presented in this paper builds around the dynamic programmability of a single DSP48E1 primitive, with minimal additional logic to create a general purpose processor supporting a full instruction-set architecture. The result is a very compact, fast processor that can execute a full gamut of general machine instructions. We show a number of simple applications compiled using a MIPS compiler, and translated to the iDEA instruction set, comparing with a Xilinx MicroBlaze, to show estimated performance figures. Being based on the DSP48E1, this processor can be deployed across next-generation Xilinx Artix-7, Kintex-7, Virtex-7, and Zynq families