Design methodology of a 28 nm FD-SOI Capacitive Feedback RF LNA based on the ACM Model and Look-up Tables

International audienceThe race to reduce the size and improve power consumption in new transistor technologies has given rise to design trade-offs that are difficult to address with standard methodologies that require an iterative process. This paper proposes a design methodology based on the ACM model and look-up tables to quickly size a 28 nm FD-SOI RF LNA. The design incorporates different tuning knobs that can be useful for optimizing design constraints and, in particular, adapting the circuit performances at very low temperatures.</p

Noise modeling using look-up tables and DC measurements for cryogenic applications

International audienceThere is today a lack of mature transistor-level compact models for the simulation of integrated circuits at cryogenic temperatures. This is particularly the case for the simulation of the noise behavior which is critical for most applications. In this paper, we aim at an efficient prediction of the white noise behavior of basic amplifying stages working at RF frequencies and cryogenic temperatures. For this, we propose the use of DC measurements that are incorporated in a Look-Up Table (LUT) and fed to a mathematical noise model. We illustrate the approach for the case of a transistor in common source configuration. The results of circuit simulation of the noise parameters in the standard temperature range are very close to the estimation of the same parameters using the LUT with just DC measurements. The approach can be readily extended to the analysis of circuits with multiple components. Next, the LUT approach is used for estimating the noise parameters at cryogenic conditions, considering DC measurements that have been carried out at these temperatures. The paper illustrates the feasibility of carrying out a cryogenic design using a LUT-based approach while accurate compact models are not yet available