Asymmetrically strained all-silicon multi-gate n-Tunnel FETs

This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4–5 GPa peak of lateral uniaxial tensile stress in the Si NW

A new definition of threshold voltage in Tunnel FETs

This work reports on the physical definition and extraction of threshold voltage in Tunnel FETs (field effect transistors) based on numerical simulation data. It is shown that the Tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, VTG, and one in terms of drain voltage, VTD. These threshold voltages can be physically defined based on the transition between a quasi-exponential dependence, and a linear dependence of the drain current on VGS or VDS, and by extension, on the saturation of the tunneling energy barrier width narrowing. The extractions of VTG and VTD are performed based on the transconductance change method in the double gate Tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these Tunnel FETs' threshold voltages, as well as the dependence of VTG on applied drain voltage and VTD on applied gate voltage, are investigated

Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs

In this letter, we propose a lateral asymmetric strain profile in a silicon nanowire or ultrathin silicon film as a key technology booster for the performance of all-silicon Tunnel FETs. We demonstrate by simulation that a Gaussian tensile-strain profile with a maximum placed at the source side of a nanowire Tunnel FET with a 50-nm channel length provides an optimized solution for a low-standby-power switch. This leads to the following: 1) ultralow I-off (more than three decades lower than in the case of a device on uniformly strained silicon); 2) boosting of I-on (more than one decade higher compared to a silicon reference); and 3) an average subthreshold swing S-avg of 48 mV/dec at room temperature. Furthermore, the inherent finite drain threshold voltage of the Tunnel FET, which could be a disadvantage for logic design with Tunnel FETs, is exponentially reduced with the strain-induced bandgap shrinkage at the source side

Small slope micro/nano-electronic switches

This paper discusses three categories of small slope electronic switches: the Tunnel FET the IMOS and the NEM-FET which are expected to bring added value compared to CMOS by presenting an abrupt subthreshold slope, smaller than the physical limit, 60mV/decade, of the solid-state MOS transistor at room temperature. Recent results and future promises are reported

The Hysteretic Ferroelectric Tunnel FET

We present the fabrication and the electrical characterization of ferroelectric tunnel FETs (Fe-TFETs). This novel family of hysteretic switches combines the low subthreshold power of band-to-band tunneling devices with the retention characteristics of Fe gate stacks, offering some interesting features for future one-transistor (1T) memory cells. We report I-on/I-off larger than 10(5) and I-off on the order of 100 fA/mu m in micrometer-scale p-type Fe-TFETs fabricated on ultrathin-film (fully depleted) silicon-on-insulator substrates with a SiO2/Al2O3/PVDF gate stack processed at low temperature. The hysteretic characteristics of the TFETs with Fe gate stacks are revealed by static experiments, and the principle of the proposed device is further confirmed by 2-D calibrated numerical simulations. Low temperature measurements down to 77 K confirm the reduced sensitivity of the TFET subthreshold swing to temperature and distinguish them from fabricated reference Fe metal-oxide-semiconductor FETs. Finally, we investigate the potential of Fe-TFETs as 1T memory devices and find retention times on the order of a few minutes at room temperature