Protective redundancy overhead reduction using instruction vulnerability factor

Due to modern technology trends, fault tolerance (FT) is acquiring an ever increasing research attention. To reduce the overhead introduced by the FT features, several techniques have been proposed. One of these techniques is Instruction-Level Fault Tolerance Configurability (ILCOFT). ILCOFT enables application developers to protect different instructions at varying degrees, devoting more resources to protect the most critical instructions, and saving resources by weakening protection of other instructions. It is, however, not trivial to assign a proper protection level for every instruction. This work introduces the notion of Instruction Vulnerability Factor (IVF), which evaluates how faults in every instruction affect the final application output. The IVF is computed off-line, and is then used by ILCOFT-enabled systems to assign the appropriate protection level to every instruction. IVF releases the programmer from the need to assign the necessary protection level to every instruction by hand. Experimental results demonstrate that IVF-based ILCOFT reduces the instruction duplication performance penalty by up to 77%, while the maximum output damage due to undetected faults does not exceed 0.6% of the total application output.EC/FP6/027648/EU/Scalable Computer Architecture/SAR

Instruction-Level Fault Tolerance Configurability

Abstract—Fault tolerance (FT) is becoming increasingly important in computing systems. FT features are based on some form of redundancy, which adds a significant cost to a system, either increasing the required amount of hardware resources or degrading performance. To enable a user to choose between stronger FT or performance, some schemes have been proposed, which can be configured for each application to use the available redundancy to increase either reliability or performance. We propose to have an instruction-level, rather than application-level, configurability of this kind, since some applications (for example, multimedia) can have different reliability requirements for their different parts. We propose to apply weaker (or no) FT techniques to the less critical parts. This yields a certain time or resource gain, which can be used to apply stronger FT techniques to the more critical parts, thereby, increasing the overall FT. We show how some existing FT techniques can be adapted to support instructionlevel FT configurability, and how a programmer can specify the desired FT of particular instructions or blocks of instructions in assembly or in a high-level programming language. In some cases compiler can assign the FT level to instructions automatically. Experimental results demonstrate that reducing the FT of noncritical instructions can lead to significant performance gains compared to a redundant execution of all the instructions. The fault coverage of this scheme is also evaluated, demonstrating that it is very application-specific. For some applications the fault coverage is very admissible, but unacceptable for others. I

Optimisation of Multimedia Applications for the

Libavcodec is an open source library that contains many different audio/video codecs, including a very fast MPEG4 codec. It has been optimised for several multimedia extensions such as Intel’s MMX, AMD’s 3DNow, etc. Wasabi is a chip multiprocessor targeted at media applications. It is being developed at Philips. Wasabi consists of several TriMedia DSPs and one or more general-purpose CPUs. The TriMedia is a VLIW processor that supports many media operations. This project is focused on (1) porting libavcodec to the TriMedia, (2) improvement of its performance by applying architecture-specific optimisations, (3) parallelisation of libavcodec, and (4) providing an interface between the TriMedia(s) executing libavcodec and the general-purpose processor(s) running application(s) that use libavcodec. First we describe how libavcodec was ported to the TriMedia. Libavcodec supports only the most recent gcc compilers, whereas th

Functional Unit Sharing Between Stacked Processors in 3D Integrated Systems

Abstract-The emerging Through Silicon Via (TSV) based 3D integration technology provides the means to stack two or more dies, enabling a low-latency interface between them. Apart of the immediate advantages of such an approach, e.g., short wires, it also opens research avenues for 3D organizations of computation platforms. In this line of reasoning we propose in this paper to share resources between stacked processors while focusing on Functional Units (FUs) inter-die sharing. The purpose of FU sharing is two fold: (i) it enables inexpensive fault tolerance by allowing, when possible, redundant instruction execution on idle FUs of processors located on other stack dies; and (ii) it can result in performance improvements by remotely executing instructions on idle FUs located on other dies in the 3D stack, when more instructions than locally available FUs are issuable. We evaluated the potential implications of our proposal on a 3D system built with two stacked processors (dies). In this case only a limited error detection capability is enabled and the experimental results indicate that our scheme covers on average 46% of the executed instructions. When performance improvement is targeted an average speedup of 6.9% can be achieved for the applications running on the considered two die stack