High Accuracy 65nm OPC Verification: Full Process Window Model vs. Critical Failure ORC

It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window [1]. However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study

Contrôle et amélioration de la robustesse des corrections de proximité optique pour les générations de circuits intégrés sub-100nm

Le leitmotiv de l'industrie des semiconducteurs est d'intégrer toujours plus de transistors sur une surface constante. La réduction des dimensions permet de produire des circuits réalisant des tâches plus complexes, plus rapidement et à moindre coût. L'étape clé de la miniaturisation est la lithographie optique par projection. Toutefois, en réduisant les largeurs des transistors et l'espace entre eux, on augmente la sensibilité du transfert à, ce que l'on appelle, les effets de proximité optique. Les techniques de correction des effets de proximité (OPC) sont largement utilisées pour améliorer l'impression des motifs des générations lithographiques avancées. Dans le même temps, les fenêtres de procédé utiles diminuent. Dans ce contexte, il devient primordial de pouvoir contrôler et améliorer la robustesse des motifs post-OPC à l'impression dans la fenêtre de procédé. Trois techniques ont été développées. Tout d'abord, des modèles calibrés dans la fenêtre de procédé sont présentés et utilisés pour le contrôle de la qualité du transfert des motifs dans la résine. Ils permettent d'appréhender les variations de dimensions des motifs soumis à des variations de dose ou de focus. Une méthodologie statistique est également mise en place dans le même but. L'intérêt de cette technique est qu'elle ne nécessite qu'une simulation pour obtenir l'information sur le pincement ou le pontage de plots de résine dans la fenêtre de procédé. Elle peut également être facilement intégrée dans le cycle d'OPC pour corriger les défauts détectés. Enfin, une nouvelle technique, appelée énergie locale, est mise en place pour le contrôle et le placement des motifs non résolus. Cette méthode est une généralisation du concept d'isofocale. Elle permet, au prix d'une seule simulation, de connaître la robustesse des motifs vis-à-vis d'un décalage en focus. Son utilisation a permis d'améliorer le placement des motifs non résolus sur les circuits complexes bidimensionnelsThe dominant recurring theme in the semiconductor industry is the necessity to integrate an increasing number of transistors in the same surface area. This reduction in dimensions makes it possible to produce circuits capable of more complex tasks, operating at increased speed and at a lower cost. The key process step in this miniaturization is optical projection lithography. However, by reducing the widths of the transistors and the spaces between them, we increase the sensitivity of the transfer to optical proximity effects. "Optical proximity correction" (OPC) techniques are necessary to improve the printability of patterns for the advanced lithographic generations. ln this context, it becomes paramount to be able to control and improve the robustness of post-OPC pattern printability throughout the process window. Three techniques were developed. First, models calibrated through the process window are presented and used in the quality control of the patterning in resist. They make it possible to understand the variation of the dimensions of patterns subjected to variations of dose and focus. Second, a statistical methodology was developed with the same aim. The interest of this technique is that it requires only one simulation to obtain information regarding the pinching or bridging of the resist in the process window. It can also be easily integrated into the OPC flow to correct detected defects. Lastly, a new technique, called local energy, has been introduced for the control and placement of assist features. This method is a generalization of the concept of isofocal printing. It allows, with only one simulation, to know the robustness of patterns with respect to defocus. Its use improves the placement of assist features in generalized two dimensional complex circuitsGRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

Process Window OPC Verification: Dry versus Immersion Lithography for the 65 nm node

Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. To verify the printability of a design across process window, compact optical models similar to those used for standard OPC are used. These models are calibrated from experimental data measured at the limits of the process window. They are then applied to the design to predict potential printing failures. This approach has been widely used for dry lithography. With the emergence of immersion lithography in production in the IC industry, the predictability of this approach has to be validated on this new lithographic process. In this paper, a comparison between the dry lithography process model and the immersion lithography process model is presented for the Poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two processes are compared with experimental results. A comparison in terms of process performance will also be a part of this study

Through-process window resist modelling strategies for the 65 nm node

Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification methods have become indispensable tools for avoiding pattern printing issues. The majority of these methods are primarily based on lithographic simulations of pattern printing behaviour across dose and focus variations. The models used for these simulations are compact optical models combined with one single resist model. Even if very predictive resist models exist, they have often a large number of parameters to fit and suffer from long computing times to execute the simulations. Simplified resist models are thus needed to enhance run-time computing during simulation. The objective of this study is to test the predictability of such resist models across the process window. Two different resist models will be considered in this study. The first resist model is a pure variable threshold resist model. The second resist modelling approach is a simplified physical model which uses Gaussian convolutions and a constant threshold to model resist printing behaviour. The study concentrates on poly layer patterning for the 65 nm node. Examples of specific simulations obtained with the two different techniques are compared against experimental results