Ionizing radiation e\ufb00ects in nanoscale CMOS technologies exposed to ultra-high doses

This thesis studies the e\ufb00ects of radiation in nanoscale CMOS technologies exposed to ultra-high total ionizing doses (TID), up to 1 Grad(SiO2). These extreme radiation levels are orders of magnitude higher that those typically experienced by space applications (where radiation e\ufb00ects in electronic are of concern). However, they can be found in some speci\ufb01c applications like the large-hadron-collider (LHC) of CERN, and, in particular, in its future upgrade, the high-luminosity LHC (HL-LHC). The study at such high doses has both revealed new phenomena, and has contributed to a better understanding of some of the already known radiation-induced e\ufb00ects. The radiation response of four di\ufb00erent CMOS technology nodes, i.e., 130, 65, 40 and 28 nm, coming from di\ufb00erent manufacturers, has been investigated in di\ufb00erent conditions of temperature, bias, dose-rate and for di\ufb00erent transistor\u2019s sizes, providing an unique and comprehensive set of data about the ultra-high TID-induced phenomena in modern CMOS technologies. This study has con\ufb01rmed that the thin gate oxide of nanoscale technologies is extremely robust to radiation, even at ultra-high doses. The main cause of performance degradation has been identi\ufb01ed in the presence of auxiliary oxides such as shallow trench insulation oxides (STI) and spacers. Both radiation-induced drain-to-source leakage current increase and radiation-induced narrow channel e\ufb00ect (RINCE) are caused by positive charge trapped in the STI. In this work, thanks to exposures to very high TID levels and to measurements performed in di\ufb00erent conditions of temperature and bias, we show that the two e\ufb00ects are provoked by charge trapped in di\ufb00erent locations along the trench oxide. Moreover, a new unexpected ultra-high-dose drain current increase (UCLI) e\ufb00ect, a\ufb00ecting narrow and long nMOS transistors, has been observed. In-depth studies of the radiation-induced short channel e\ufb00ect (RISCE), related to the presence of the spacers, have shown that, at ultra-high doses, the degradation mechanism consists of two phases. A \ufb01rst increase of the series resistance, caused by the radiation-induced charge trapping in the spacers, is followed by a threshold voltage shift provoked by the transport of hydrogen ions from the spacers to the gate oxide. This model has been validated by several static measurements, TCAD simulations and charge pumping measurements. The dependencies of these e\ufb00ects on bias, temperature and size of the transistors have also been studied in detail. Moreover, an unexpected true dose-rate sensitivity has been measured in both nMOS and pMOS transistors in 65 and 130 nm technologies, although the radiation response of MOS devices is considered insensitive to true dose-rate e\ufb00ects. The current degradation in samples irradiated at a dose-rate comparable to that expected in the HL-LHC is larger by a factor of 3c2 than that measured in the typical quali\ufb01cation test, usually carried out with a much higher dose-rate. This is clearly of serious concern for the quali\ufb01cation of circuits designed for the particle detectors of the HL-LHC

GigaRad total ionizing dose and post-irradiation effects on 28 nm bulk MOSFETs

The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS technology in the forthcoming upgrade of the Large Hadron Collider at CERN. The total ionizing dose effects show limited influence in the drive current of all the tested nMOSFETs. Nonetheless, the leakage current increases significantly, affecting the normal device operation of the nMOSFETs. These phenomena can be linked to the charge trapping in the oxides and at the Si/oxide interfaces, related to both the gate oxide and the shallow trench isolation oxide. In addition, it has been observed that the radiation-induced effects are partly recovered by the long-term post-irradiation annealing. To quantify the total ionizing dose effects on DC characteristics, the threshold voltage, subthreshold swing, and drain induced barrier lowering have also been extracted for nMOSFETs

A generalized EKV charge-based MOSFET model including oxide and interface traps

This paper presents a generalized EKV charge-based MOSFET model that includes the effects of trapped charges in the oxide bulk and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions for the mobile charge density and the drain current. These simple formulations demonstrate the effects of charge trapping on MOSFET characteristics and crucial device parameters. The proposed charge-based analytical model, including the effect of velocity saturation, is successfully validated through measurements performed on devices from a 28-nm bulk CMOS technology. Ultrahigh total ionizing doses up to 1 Grad(SiO$_2$) are applied to generate oxide-trapped charges and activate passivated interface traps. Despite a small number of parameters, the model is capable of accurately capturing measurement results over a wide range of device operation from weak to strong inversion. Explicit expressions of device parameters also allow for the extraction of the oxide- and interface-trapped charge densities

Forward and Reverse Operation of Enclosed-Gate MOSFETs and Sensitivity to High Total Ionizing Dose

Frond-end electronics at the High Luminosity-Large Hadron Collider (HL-LHC) at CERN, will be exposed to ten-fold radiation doses. The use of enclosed gate (EG) MOSFETs of 65 nm Bulk CMOS process, is considered to be a viable solution in order to suppress performance degradation effects that occur after high TID exposure. The present paper presents a detailed analysis of the functionality of EG MOSFETs operating under high TID, taking into accountspecific layout characteristics

Charge Buildup and Spatial Distribution of Interface Traps in 65-nm pMOSFETs Irradiated to Ultrahigh Doses

In this paper, a commercial 65-nm CMOS technology is irradiated at ultrahigh ionizing doses and then annealed at high temperature under different bias conditions. The experimental results demonstrate the high sensitivity of pMOSFETs to radiation-induced short-channel effects, related to the buildup of defects in spacer dielectrics. We find that the charge buildup in the spacers is insensitive to the applied source-to-drain electric field, but the generation and/or annealing of interface traps strongly depends on applied drain bias and channel length. The static dc and charge-pumping measurements indicate a high density of interface traps in the lateral source/drain extension regions. The worst case bias condition corresponds to the application of a large drain-source voltage, due to the lateral electric field driving hydrogen from the spacers toward the source extension and the channel. The consequent differences in growth and annealing rates of interface traps lead to a large asymmetric degradation of the short-channel transistors. The technology computer-aided design simulations are used to qualitatively confirm the proposed degradation model

Characterization and Modeling of GigaRad-TID-Induced Drain Leakage Current in a 28 nm Bulk CMOS Technology

This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of n MOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual n MOSFETs of various sizes provide insight into the TID-induced lateral parasitic devices, which contribute the most to the significant increase up to four orders of magnitude in the drain leakage current. We introduce a semiempirical physics-based approach using only three parameters to model the parallel parasitic and total drain leakage current as a function of TID. Taking into account the gate independence of the drain leakage current at high TID levels, we model the lateral parasitic device as a gateless charge-controlled device by using the simplified charge-based Enz-Krummenaker-Vittoz (EKV) MOSFET model. This approach enables us to extract the equivalent density of trapped charges related to the shallow trench isolation oxides. The adopted simplified EKV MOSFET model indicates the weak inversion operation of the lateral parasitic devices