New breakdown mechanism investigation: barrier metal penetration induced soft breakdown in low-k dielectrics

© 2016 IEEE. A Soft Breakdown (SBD) phenomenon happening in porous low-k dielectrics during time dependent dielectric breakdown measurements was investigated. The early formation of local conductive paths was identified by monitoring leakage currents and capacitance data in the SBD phase. The nature of this conductive path was demonstrated to be related to intrinsic dielectric degradation. By comparing samples with different process conditions, we found that barrier metal penetration is an important root cause of SBD initiation. Our study of the voltage and temperature acceleration of the SBD phenomenon shows that these acceleration factors, m=22 and Ea=0.2eV, are at a reasonable level. However, further investigations on large size devices illustrate that the difference in barrier metal penetration depth between different samples could lead to a large decrease of Weibull slopes and degrade the overall reliability performance. Therefore, innovations of metal barrier deposition on porous low-k dielectrics to avoid barrier metal penetration are required for advanced technology nodes.status: publishe

Alternative integration of ultra low-k dielectrics by template replacement approach

© 2015 IEEE. Replacement of sacrificial template by ultralow-k dielectric was studied as an alternative integration approach for Cu/low-k interconnect. Metallization structure was first formed by patterning a template material. After template removal, a spin-on porous low-k was deposited on the metal lines. Then, planarization of the excess low-k was performed by CMP. The proposed approach does solve the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous structures.status: publishe

Optimization and upscaling of spin coating with organosilane monolayers for low-k pore sealing

© 2016 Elsevier B.V. For porous low-k film to be integrated into the next generation of interconnects, the pores need to be sealed against metal ions and barrier precursors. Self-assembled monolayers (SAMs) from organosilane precursor are spin coated onto 300 mm k = 2.2 low-k wafers. Two solvents, propylene glycol monomethyl ether acetate (PGMEA) and methanol with different dielectric constant of 8.3 and 20.1, are evaluated in terms of SAMs layer quality and sealing efficiency at coupon level. SAMs deposited from PGMEA show better sealing than SAMs deposited from methanol and therefore are selected for upscaling. Full wafer spin coating results show that a concentration of 0.05 mM or below results in a partial coverage and a tilt angle as high as 70° from the backbone to the normal. Aggregation is observed for all tested concentrations and is worse for higher concentrations, which is possibly induced by the non-negligible presence of water in PGMEA solvents. In order to test the sealing efficiency of the SAMs layer against metal barrier precursors, MnN films by chemical vapor deposition (CVD) and TaNx/Ta (TNT) films by physical vapor deposition (PVD) are deposited on SAM coated low-k wafers. HfO2is also deposited by Atomic layer deposition (ALD), which is not considered as a barrier but to test the sealing against ALD precursors. Depth profiling Rutherford Backscattering Spectrometry (RBS) measurements indicate an effective sealing of SAMs against CVD and ALD precursors but not against PVD barrier.status: publishe

Correlation between stress-induced leakage current and dielectric degradation in ultra-porous SiOCH low-k materials

© 2015 AIP Publishing LLC. Stress-Induced Leakage Current (SILC) behavior during the dielectric degradation of ultra-porous SiOCH low-k materials was investigated. Under high voltage stress, SILC increases to a critical value before final hard breakdown. This SILC increase rate is mainly driven by the injected charges and is negligibly influenced by temperature and voltage. SILC is found to be transient and shows a t-1 relaxation behavior, where t is the storage time at low voltages. This t-1 transient behavior, described by the tunneling front model, is caused by both electron charging of neutral defects in the dielectric close to the cathode interface and discharging of donor defects close to the anode interface. These defects have a uniform density distribution within the probed depth range, which is confirmed by the observed flat band voltage shift results collected during the low voltage storage. By applying an additional discharging step after the low voltage storage, the trap energies and spatial distributions are derived. In a highly degraded low-k dielectric, the majority of defects have a trap depth between 3.4 eV and 3.6 eV and a density level of 1 × 1018eV-1cm-3. The relation between the defect density N and the total amount of the injected charges Q is measured to be sub-linear, N ∼ Q0.45±0.07. The physical nature of these stress-induced defects is suggested to be caused by the degradation of the Si-O based skeleton in the low-k dielectric.status: publishe

Alternative metals for advanced interconnects

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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

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