A δ∑ Dithering-Amplification-Based Identification Technique for Online SMPS

A novel nonparametric system identification (SI) algorithm is described, focusing on PID-based control loops for buck converters with effective series resistance (ESR) in the output filter. Dithering amplification effects on the control path are exploited during the steady-state converter operation. The noise injected is used to stimulate the loop reaction and to identify the output filter configuration. Oversampling-dithering features of third-order δ σ modulators are used to increase the DPWM resolution during the converter nominal operation and, moreover, as the core key to compute the SI algorithm. A modified structure of a noise shaper is used to handle the resolution of the SI algorithm over a range of the desired frequencies during the nonparametric identification. The SI algorithm comprises two steps: The first processing step extracts the resonant frequency, and the second extracts the ESR zero from the power spectrum density computation of the control feedback error. The SI method has been validated with different buck converter configurations, and has successfully been integrated and measured into a digitally controlled buck converters prototype for automotive safety application

Scalable hybrid CORDIC-LUT architectures for CG-FFT processors

In this work we introduce Processing Element (PE) scalability in twiddle factor generators for FFT processors. First the twiddle factor indexing scheme for Constant Geometry FFT is analyzed and a CORDIC-based novel algorithm is deduced. It uses single-step rotations and does not need any CORDIC gain correction. Then, two architectures implementing the algorithm are presented with the goal of scalability. The first (shared core) is characterized by both low register count and variable throughput, while the second (pipelined) achieves the maximum throughput during the whole computation. Our hybrid models use both one ROM and multiplier-based CORDIC modules. The designs are then evaluated in terms of register usage and output error, showing scalability of register bits as a function of the number of PEs if compared to other architectures. Architectures were coded in VHDL and synthesized on a Xilinx Virtex-5 330T FPGA

Prototype of a novel steady-state load identification technique for digitally controlled DC-DC power supplies

This demo will show a novel method of Selftuning technique suitable for digitally controlled Switching Mode Power Supplies (SMPS). Perturbations can be added in order to stimulate loop reaction, which mainly contains load information. Variations on the Power Supply output filter, can be monitored and regulation gains can be consequently set for reaching a well compensated closed loop condition. The closed-loop system can be periodically perturbed by injecting a further amount of quantization noise provided through a low-resolution Delta-Sigma (ΔΣ) modulator. Digital control, PSD computation and Extraction-regulation blocks are synthesized on Virtex6 FPGA, while analog blocks (Buck Converter and ADC) are part of a Test Chip (TC) which can be configured via SPI in order to enable an external control loop configuration

A Reconfigurable Switched Capacitor DC-DC Converter with 1.9-6.3-V Input Voltage Range and 85 Peak Efficiency in 28-nm CMOS

A reconfigurable step-down switched capacitor dc-dc converter (SCC) capable of operating over a wide input voltage range from 1.9 to 6.3 V is presented in this letter. The converter can be reconfigured in five different topologies, obtaining five different voltage conversion ratios, with a minimum overhead in terms of extra switches and flying capacitors. Prototypes implemented in a 28-nm CMOS technology can deliver up to 0.45-W output power while regulating the output voltage to 0.9 V with a 85 peak efficiency

Valutazione sperimentale della contaminazione ambientale da metalli in un'area industrializzata della Sardegna

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