22 research outputs found
Power Efficient UART Design Using Capacitive Load on Different Nanometer Technology FPGA
No full textDifferent I/O Standard and Technology Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green Wireless Communication on FPGA
No full textI/O Standard Based Thermal/Energy Efficient Green Communication For Wi-Fi Protected Access on FPGA
No full textInput/output Buffer based Vedic Multiplier Design for Thermal Aware Energy Efficient Digital Signal Processing on 28nm FPGA
No full textHustle and frequency analysis based High speed and energy efficient art Design on spartan-6 fugal
No full textEnergy Efficient and High–Performance FIR Filter Design on Spartan–6 FPGA
No full textIn this paper, we are going to design the energy efficient Gaussian low pass FIR filter on spartan-6 FPGA. To make an energy efficient filter, we have used different methods in this paper like capacitance scaling, frequency scaling, and then we analysed the demand of power by Gaussian low pass FIR filter. The frequency range which is used in this paper is 1 GHz, 2GHz, 2.5GHz, 5 GHz, 10 GHz and the range of capacitance which we have used un this paper is 5pF, 10pF, 25pF, 40pF and 50 pF. An FIR filter always remnants in linear phase with the help of symmetric co-efficient and this is the very useful feature of the FIR filter for phase sensitive application like data communications etc. At present there are many different methods for communications and networking. So, in this paper, we have designed an energy efficient FIR filter and that design will faster than traditional design
