A CMOS Imager with PFM/PWM Based Analog-to-digital Converter

An on-pixel analog-to-digital converter based on both PFM and PWM schemes is reported. The proposed architecture uses a limited number of transistors that can be implemented in a small silicon area resulting in a 23% fill-factor. The digital sensor can be externally configured in order to operate under either the PFM or PWM scheme. At high light intensities, the PFM scheme is replaced by the PWM scheme which proves to be much more efficient in terms of power consumption and clock frequency requirements. An in-built light adaptation mechanism has also been implemented which allows the sensor to better adapt to low-light intensity or to adjust the sensor saturation level. As a consequence, the sensor features a programmable dynamic range. Image lag is reduced in both schemes since a reset of the photodetector is performed after the conversion period. The pixel based ADC has been designed and fabricated using CMOS 0.25 μm technology

A committee machine gas identification system based on dynamically reconfigurable FPGA

This paper proposes a gas identification system based on the committee machine (CM) classifier, which combines various gas identification algorithms, to obtain a unified decision with improved accuracy. The CM combines five different classifiers: K nearest neighbors (KNNs), multilayer perceptron (MLP), radial basis function (RBF), Gaussian mixture model (GMM), and probabilistic principal component analysis (PPCA). Experiments on real sensors' data proved the effectiveness of our system with an improved accuracy over individual classifiers. Due to the computationally intensive nature of CM, its implementation requires significant hardware resources. In order to overcome this problem, we propose a novel time multiplexing hardware implementation using a dynamically reconfigurable field programmable gate array (FPGA) platform. The processing is divided into three stages: sampling and preprocessing, pattern recognition, and decision stage. Dynamically reconfigurable FPGA technique is used to implement the system in a sequential manner, thus using limited hardware resources of the FPGA chip. The system is successfully tested for combustible gas identification application using our in-house tin-oxide gas sensors

Quantum Parametric Amplification and NonClassical Correlations due to 45 nm nMOS Circuitry Effect

This study unveils a groundbreaking exploration of using semiconductor technology in quantum circuitry. Leveraging the unique operability of 45 nm CMOS technology at deep cryogenic temperatures (~ 300 mK), a novel quantum electronic circuit is meticulously designed. Through the intricate coupling of two matching circuits via a 45 nm nMOS transistor, operating as an open quantum system, the circuit quantum Hamiltonian and the related Heisenberg-Langevin equation are derived, setting the stage for a comprehensive quantum analysis. Central to this investigation are three pivotal coefficients derived, which are the coupling between the coupled oscillator charge and flux operators through the internal circuit of the transistor. These coefficients emerge as critical determinants, shaping both the circuit potential as a parametric amplifier and its impact on quantum properties. The study unfolds a delicate interplay between these coefficients, showcasing their profound influence on quantum discord and the gain of the parametric amplifier. Consequently, the assimilation of 45 nm CMOS technology with quantum circuitry makes it possible to potentially bridge the technological gap in quantum computing applications, where the parametric amplifier is a necessary and critical device. The designed novel quantum device serves not only as a quantum parametric amplifier to amplify quantum signals but also enhances the inherent quantum properties of the signals such as non-classicality. Therefore, one can create an effective parametric amplifier that simultaneously improves the quantum characteristics of the signals. The more interesting result is that if such a theory becomes applicable, the circuit implemented in the deep-cryogenic temperature can be easily compatible with the next step of circuitry while keeping the same electronic features compatibility with the quantum processor.Comment: 11 pages, 5 figure

A compact multi-chip-module implementation of a multi-precision neural network classifier

This paper describes a novel MCM digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7 μm technolog

A wide dynamic range cmos imager with extended shunting inhibition image processing capabilities

A CMOS imager based on a novel mixed-mode VLSI implementation of biologically inspired shunting inhibition vision models is presented. It can achieve a wide range of image processing tasks such as image enhancement or edge detection via a programmable shunting inhibition processor. Its most important feature is a gain control mechanism allowing local and global adaptation to the mean input light intensity. This feature is shown to be very suitable for wide dynamic range imager

Smart Manufacturing Technologies for Printed Electronics

Fabrication of electronic devices on different flexible substrates is an area of significant interest due to low cost, ease of fabrication, and manufacturing at ambient conditions over large areas. Over the time, a number of printing technologies have been developed to fabricate a wide range of electronic devices on nonconventional substrates according to the targeted applications. As an increasing interest of electronic industry in printed electronics, further expansion of printed technologies is expected in near future to meet the challenges of the field in terms of scalability, yield, and diversity and biocompatibility. This chapter presents a comprehensive review of various printing electronic technologies commonly used in the fabrication of electronic devices, circuits, and systems. The different printing techniques based on contact/noncontact approach of the printing tools with the target substrates have been explored. These techniques are assessed on the basis of ease of operation, printing resolutions, processability of materials, and ease of optimization of printed structures. The various technical challenges in printing techniques, their solutions with possible alternatives, and the potential research directions are highlighted. The latest developments in assembling various printing tools for enabling high speed and batch manufacturing through roll-to-roll systems are also explored

FPGA implementation of a predictive vector quantization image compression algorithm for image sensor applications

This paper presents a hybrid image compression scheme based on a block based compression algorithm referred to as Vector Quantization (VQ) combined with the Differential Pulse Code Modulation (DPCM) technique. The proposed image compression technique called the PVQ scheme results in enhanced image quality as compared to the standalone VQ. The generated codebooks for the PVQ scheme are more robust for image coding than that of the VQ. This made our system a suitable candidate for developing on chip image sensor with integrated data compression processor. The proposed system was validated through FPGA implementation. The resulting implementation achieved good compression and image quality with moderate system complexity

Comparison of reconfigurable structures for flexible word-length multiplication

Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. <br><br> In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved