Statistical Delay Calculation

This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new scheme to perform the delay calculations with stochastic delay values. From a mathematical analysis some counter--intuitive properties of delays in the presence of uncertain delay values are shown. The results section shows that that traditional worst-- case timing analysis is on average 21% too pessimistic for the set of IWLS '91 combinational benchmark circuits. Also, it is shown that the traditional typical delay calculation underestimates the most likely circuit delay by 0 -- 14%. Furthermore, due to the mathematical properties of the delay calculations, the uncertainty in the delay of a circuit is usually much smaller than the uncertainty in t..

Analyzing Delay Uncertainties: Statistical Delay Calculation

This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new scheme to perform the delay calculations with stochastic delay values. From a mathematical analysis some counter-intuitive properties of delays in the presence of uncertain delay values are shown. The results section shows that that traditional worst-case timing analysis is on average 21% too pessimistic for the set of IWLS '91 combinational benchmark circuits. Also, it is shown that the traditional typical delay calculation underestimates the most likely circuit delay by 0 - 14%. Furthermore, due to the mathematical properties of the delay calculations, the uncertainty in the delay of a circuit is usually much smaller than the uncertainty in the d..

A New Algorithm to Create Prime Irredundant Boolean Expressions

This paper describes a new, efficient algorithm to make Boolean sum--of--cubes expressions prime and irredundant. A description of the logic function of a combinational logic circuit in terms of prime and irredundant expressions is a solid basis for the synthesis of fully testable logic circuits, as was recently shown in [HAC89] and [HAC92]. We have, therefore, developed an efficient recursive algorithm, based on Shannon expansion. Expressions are first expanded until the leaves are unate expressions. These can be made prime and irredundant by just checking for single cube containment [BRA84]. Then, the expression has to be reassembled, by merging the expanded results. By carefully exploiting the properties of Shannon expansion, we have been able to find a merging procedure, by which the primeness and irredundancy of the children are retained, while performing only a minimum number of containment tests. Using the algorithm on the MCNC benchmark set shows, that the algorithm is very eff..

A Linear Programming Approach for the Estimation of an Upper Bound on the Maximum Power of CMOS Circuits

Maximum instantaneous power in VLSI circuits is of great importance to the design of power and ground lines in a VLSI circuit. Underestimating the maximum instantaneous power greatly reduces the circuits reliability. An accurate estimate of the maximum instantaneous power is therefore needed. Unfortunately, finding the input vectors which give the maximum power consumption is a combinational problem. An exhaustive search is very CPU-time intensive even for small circuits with few primary inputs. We therefore propose a novel linear programming approach, using variables denoting switching scenarios, instead of logic levels between possible switching events, to estimate an upper bound on the maximum power consumption in a CMOS circuit under an input vector change. We present results demonstrating the approach and discuss the benefits and limitations of three linear programming solvers for our type of linear programming problem. I. Introduction Maximum instantaneous power in VLSI circuits..

Efficient Orthonormality Testing for Synthesis with Pass-Transistor Selectors

This paper presents the mapping problem for pass transistor selector mapping, which has not been addressed before. Pass transistor synthesis is potentially important for semi- or full-custom design techniques, which are increasingly attracting attention. Pass transistors have the advantage that fewer transistors are needed, and that circuits with high fanin and small delay can be constructed. Technology mapping approaches in the existing literature cannot handle these selectors, due to the restriction of 1-hot encoding of the control signals. We present a new algorithm to address this problem, which is based on the novel idea of a general Boolean Oracle. Our oracle is based on ATPG techniques, and compared to BDDs, the oracle has the advantage that failure to complete only affects optimization locally, and does not hinder optimization elsewhere in the logic. A limitation of BDDs is that it is difficult to complete the algorithm if a BDD grows too large. The experimental results show up to 82%..