TWEPP 2021 Topical Workshop on Electronics for Particle Physics

The development of the MPA and SSA ASICs is approaching the production phase with a volume of more than 1000 wafers. The importance of yield management in the construction of the Outer Tracker modules requires rigorous testing methods capable to identify all defective parts. This contribution presents customized Design for Testability methods to replace the currently used functional tests that show limited coverage and long testing time. Scan-chain design, memory and Logic Built-In-Self-Test have been adapted for radiation-hard ASICs and introduced on-chip for a novel testing approach. Design flow and implementation choices will be presented together with silicon results

A simulation methodology for establishing IR-drop-induced clock jitter for high precision timing ASICs

International audienceThe combination of 3D tracking and high-precision timing measurements has been identified by the European Committee for Future Accelerators as a fundamental requirement to increase detection capabilities for future applications. Among others, on-chip high-quality clock is a key factor determining the overall resolution of timing ASICs. However, in large and dense chips, power-grid drops can severely affect the non-deterministic jitter of the clock, representing a limit to the performances. This contribution presents a simulation framework based on commercial tools to derive power supply-induced jitter, providing a pre-silicon methodology to assess its impact to timing indeterminism. The flow is presented together with practical examples and results

MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination

Particle tracking detectors for High Energy Physics need a new readout technique to cope with the increase of the collision rate foreseen for the High Luminosity LHC upgrade. In particular, the selection of interesting physics events at the first trigger stage becomes extremely challenging at high luminosity, not only because of the rate increase, but also because the selection algorithms become inefficient in high pileup conditions. A substantial increase of latency and trigger rate provides an improvement that is not sufficient to preserve the tracking performance of the current system. A possible solution consists of using tracking information for the event selection. Given a limited bandwidth, the use of tracking information for the event selection implies that the tracker has to send out self-selected information for every event. This is the reason why front-end electronics need to perform a local data reduction. This functionality relies on the capability of continuous particle discrimination on-chip based on the transverse momentum. The high complexity of the digital logic for particle selection and the very low power requirement of $$\,95\,\% in particle selection and a data reduction from $\sim$\,30\,Gbps\,/\,$\text{cm}^2$ to $\sim$\,0.7\,Gbps\,/\,$\text{cm}^2$ Two full-size and full-functionality prototypes, called MPA and SSA, have been designed, produced and tested. These two readout front-end ASICs perform binary readout of silicon modules which combine pixel and strip sensors, full-event storage with triggered readout, and continuous data selection with trigger-less readout

MPA-SSA, design and test of a 65nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination

Particle tracking detectors for High Energy Physics need a new readout technique to cope with the increase of the collision rate foreseen for the High Luminosity LHC upgrade. In particular, the selection of interesting physics events at the first trigger stage becomes extremely challenging at high luminosity, not only because of the rate increase, but also because the selection algorithms become inefficient in high pileup conditions. A substantial increase of latency and trigger rate provides an improvement that is not sufficient to preserve the tracking performance of the current system. A possible solution consists of using tracking information for the event selection.Given a limited bandwidth, the use of tracking information for the event selection implies that the tracker has to send out self-selected information for every event. This is the reason why front-end electronics need to perform a local data reduction. This functionality relies on the capability of continuous particle discrimination on-chip based on the transverse momentum.The high complexity of the digital logic for particle selection and the very low power requirement of 95% in particle selection and a data reduction from ∼30Gbps/cm$^2$ to ∼0.7Gbps/cm$^2$. Two full-size and full-functionality prototypes, called MPA and SSA, have been designed, produced and tested. These two readout front-end ASICs perform binary readout of silicon modules which combine pixel and strip sensors, full-event storage with triggered readout, and continuous data selection with trigger-less readout

Low-power SEE hardening techniques and error rate evaluation in 65nm readout ASICs

Single event radiation effects represent one of the main challenges for digital designs exposed to ionizing particles in high energy physics detectors. Radiation hardening techniques are based on redundancy, leading to a significant increase in power consumption and area overhead. This contribution will present the single event effects hardening techniques adopted in the pixel and strip readout ASICs of the PS modules for the CMS outer tracker upgrade in relation to power requirements and error rates. Cross section measurements on the silicon prototypes and expected error rates evaluated for the CMS tracker particle flux and spectrum will be presented

Study of a Triggered, Full Event Zero-Suppressed Front-End Readout Chain operating up to 1 MHz Trigger Rate and Pileup of 300 for CMS Outer Tracker upgrade at HL-LHC

International audienceThe CMS Outer Tracker at HL-LHC will have to cope with pileup of 300 events per bunch cross-ing and a trigger rate of up to 1 MHz. The front-end electronics readout chain consists of read-out ASICs connected to a data concentrator ASIC featuring zero-suppression. This contributionpresents the methodology and the analysis work for the buffer sizing and exception handling fea-turing a robust data readout synchronization, with an event loss probability lower than 0.1 % atthe highest pileup condition and a power density lower than 100 mW/cm$^2$

First results from the CIC data aggregation ASIC for the Phase 2 CMS Outer Tracker

The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase 2 CMS Outer Tracker at the High-Luminosity LHC (HL-LHC). Prototyped in a 65 nm CMOS technology, the CIC aggregates the digital data coming from eight upstream front-end chips, formatting it into data packets containing the trigger information from eight bunch crossings and the raw data from events passing the Level 1 (L1) trigger, before transmission to the lpGBT. The role of the CIC in the readout chain is to provide an extra factor of data reduction by grouping data over time and space. A first prototype, the CIC1, integrating all functionalities for system level operation, has been tested in early 2019. A brief description of the functionalities and the test results obtained concerning the performance characterization and the radiation tolerance of the chip are presented in this contribution

Strategies and performance of the CMS silicon tracker alignment during LHC Run 2

The strategies for and the performance of the CMS silicon tracking system alignment during the 2015–2018 data-taking period of the LHC are described. The alignment procedures during and after data taking are explained. Alignment scenarios are also derived for use in the simulation of the detector response. Systematic effects, related to intrinsic symmetries of the alignment task or to external constraints, are discussed and illustrated for different scenarios