Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors

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Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors

114 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1999.More specifically, we propose a technique that uses an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of the main power consumers in most of today's high-performance microprocessors. Results are reported for the SPEC95 benchmarks in the R-4400 processor which implements the MIPS2 instruction set architecture.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD

A Novel Design for Testability Technique Using State Space Information

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySamsungU of I OnlyRestricted to UIUC communit

A Novel Design for Testability Technique Using State Space Information

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySamsungU of I OnlyRestricted to UIUC communit

Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors

In this paper we propose a technique that uses an ad-ditional mini cache located between the I-Cache and the CPU core, and buffers instructions that are nested within loops and are continuously otherwise fetched from the I-Cache. This mechanism is combined with code modifications, through the compiler, that greatly sim-plify the required hardware, eliminate unnecessary in-structionfetching, and consequently reduce signal switch-ing activity and the dissipated energy. We show that the additionalcache, dubbed L-Cache, is much smaller and simpler than the I-Cache when the compiler assumes the role of allocating instructions in it. Throughsimulation, we show that, for the SPECfp95 benchmarks, the I-Cache remains disabled most of the time, and the “cheaper ” extra cache is used instead. We present experimental results that validate the effective-ness of this technique, and present the energy gains for most of the SPEC95 benchmarks.