52 km-long transmission link using a 50 Gb/s O-band silicon microring modulator co-packaged with a 1V-CMOS driver

We present an O-band silicon microring modulator with up to 50 Gb/s modulation rates, co-packaged with a 1V-CMOS driver in a dispersion un-compensated, transmission experiment through 52 km of standard single-mode fiber. The experimental results show 10(-9) error-rate operation with a negligible power penalty of 0.2 dB for 40 Gb/s and wide-open eye diagrams for 50 Gb/s data, corresponding to a record high bandwidth-distance product of 2600 Gb.km/s. A comparative analysis between the proposed transmitter assembly and a commercial LiNbO3 modulator revealed a moderate increase of 3.8 dB in power penalty, requiring only 20% of the driving voltage level used by the commercial modulator

Towards high-speed energy-efficient pulse-switching networks implemented in carrier-injection-based si-photonics

We show that carrier injection based Si-photonics modulators [1] can form the basis for building compact, low-loss and power efficient reconfigurable networks, enabling the switching of ps-pulse trains with sub-GHz repetition rates. The use of pre-emphasis-based activation [2] permits ns-scale switching transitions. Although the steady-state energy consumption in this platform is well studied, the impact of the dynamic energy consumption for these ns switching periods is not well known. Here, we show pre-emphasis-based sub-ns transitions and present a novel large-signal analysis that allows the driving scheme optimization for energy-efficient pulse switching

4-channel 200 Gb/s WDM O-band silicon photonic transceiver sub-assembly

We demonstrate a 200G capable WDM O-band optical transceiver comprising a 4-element array of Silicon Photonics ring modulators (RM) and Ge photodiodes (PD) co-packaged with a SiGe BiCMOS integrated driver and a SiGe transimpedance amplifier (TIA) chip. A 4 x 50 Gb/s data modulation experiment revealed an average extinction ratio (ER) of 3.17 dB, with the transmitter exhibiting a total energy efficiency of 2 pJ/bit. Data reception has been experimentally validated at 50 Gb/s per lane, achieving an interpolated 10E-12 bit error rate (BER) for an input optical modulation amplitude (OMA) of -9.5 dBm and a power efficiency of 2.2 pJ/bit, yielding a total power efficiency of 4.2 pJ/bit for the transceiver, including heater tuning requirements. This electro-optic subassembly provides the highest aggregate data-rate among O-band RM-based silicon photonic transceiver implementations, highlighting its potential for next generation WDM Ethernet transceivers. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

Low-power 56Gb/s NRZ microring modulator driver in 28nm FDSOI CMOS

High speed optical interconnects require low-power compact electro-optical transmit modules comprising driver circuits and optical modulators. This letter presents a low power 56 Gb/s non-return-to-zero CMOS inverter-based driver in 28 nm fully depleted silicon-on-insulator CMOS driving a 46 GHz silicon photonic microring modulator. The driver delivers 1 Vpp to the microring modulator from a 75 mVpp input while only consuming 40 mW (710 fJ/bit at 56 Gb/s). The realized transmitter shows 4 dB extinction ratio when running of a 1 V supply voltage. Transmission experiments up to 2 km of single mode fiber show a bit-error-ratio less than 1 . 10(-9) at 56 Gb/s

O-Band silicon photonic transmitters for datacom and computercom interconnects

Today, the datacenter ecosystems are fueling the demand for novel transmitter (TX) technologies complying with the off-board, on-board, and chip-to-chip computing needs. This has set a new class of requirements for the TX infrastructure that should now offer multiple credentials, namely: high-speed, O-band operation for avoiding dispersion compensation in long distances, wavelength-division multiplexing (WDM) capabilities for higher throughput and multicasting/broadcasting support, and tight copackaging with low-power electronics. Silicon (Si) photonic TXs have been extensively studied toward high-speed and WDM TX engines targeting mainly C-band. Only a limited number of Si-Pho O-band TXs have been reported, however with <= 32 Gb/s/channel line-rate capabilities and with a WDM portfolio that has not been fully explored yet. In this paper, we introduce a novel silicon photonic high-speed O-band TX hardware platform that can meet the current datacom and computercom interconnect requirements. We demonstrate a ring modulator (RM) based four-channelWDMTX at 4 x 40 Gb/s non-return-to-zero (NRZ) operation that supports wavelength parallelism in unicast operation but can also pave the way toward WDM TX engines for the post-100 GbE TX era. Moreover, we present a broadband Si Mach-Zehnder modulator employed in a WDM modulation scheme of 2 x 25 Gb/s NRZ signals and demonstrate multicasting when combined with a 8x8 passive arrayed waveguide grating router (AWGR) wavelength router, addressing the broadcasting needs of traffic usually encountered in cache-coherent multisocket settings. Finally, we further demonstrate the tight synergy of O-band Si-RM modulators with high-speed CMOS electronics, presenting an RM-based TX assembly prototype employing a fully depleted silicon-on-insulator CMOS driver, delivering 50-Gb/s NRZ operation

A 40 Gb/s chip-to-chip interconnect for 8-socket direct connectivity using integrated photonics

We present an O-band any-to-any chip-to-chip (C2C) interconnection at 40 Gb/s suitable for up to 8-socket direct connectivity in multi-socket server boards, utilizing integrated low-energy photonics for the transceiver and routing functions. The C2C interconnect exploits an Si-based ring modulator as its transmitter and a co-packaged photodiode/transimpedance amplifier enabled receiver interconnected over an 8 x 8 Si-based arrayed waveguide grating router, allowing for a single-hop flat-topology interconnection between eight nodes. A proof-of-concept demonstration of the C2C interconnect is presented at 25 and 40 Gb/s for eight possible routing scenarios, revealing clear eye diagrams at both data rates with extinction ratios of 4.8 +/- 0.3 and 4.38 +/- 0.31 dB, respectively, among the eight routed signals

400 Gb/s silicon photonic transmitter and routing WDM technologies for glueless 8-socket chip-to-chip interconnects

Arrayed Waveguide Grating Router (AWGR)-based interconnections for Multi-Socket Server Boards (MSBs) have been identified as a promising solution to replace the electrical interconnects in glueless MSBs towards boosting processing performance. In this article, we present an 8-socket glueless optical flat-topology Wavelength Division Multiplexing (WDM)-based point-to-point (P2P) interconnect pursued within the H2020 ICT project ICT-STREAMS and we report on our latest achievements in the deployment of the constituent silicon (Si)-photonic transmitter and routing building blocks, exploiting experimentally obtained performance metrics for analyzing the 8-socket chip-to-chip (C2C) connectivity in terms of throughput and energy efficiency. We demonstrate an 8-channel WDM Si-photonic microring-based transmitter (Tx) capable of providing 400 (8 x 50) Gb/s non-return-to-zero (NRZ) Tx capacity and an 8 x 8 Coarse-WDM (CWDM) Si-AWGR with verified cyclic data routing capability in O-band. Following an overview of our recently demonstrated crosstalk (XT)-aware wavelength allocation scheme, that enables fully-loaded AWGR-based interconnects even for typical sub-optimal XT values of silicon integrated CWDM AWGRs, we validate the performance of a full-scale 8-socket interconnect architecture through physical layer simulations exploiting experimentally-verified simulation models for the underlying Si-photonic Tx and routing circuits. This analysis reveals a total aggregate capacity of 1.4 Tb/s for an 8-socket interconnect when operating with 25 Gb/s line-rates, which can scale to 2.8 Tb/s at an energy efficiency of just 5.02 pJ/bit by exploiting the experimentally verified building block performance at 50 Gb/s line. This highlights the perspectives for up to 69% energy savings compared to the standard QuickPath Interconnect (QPI) typically employed in electronic glueless MSB interconnects, while scaling the single-hop flat connectivity from 4- to 8-socket interconnection systems

Silicon circuits for chip-to-chip communications in multi-socket server board interconnects

Multi-socket server boards (MSBs) exploit the interconnection of multiple processor chips towards forming powerful cache coherent systems, with the interconnect technology comprising a key element in boosting processing performance. Here, we present an overview of the current electrical interconnects for MSBs, outlining the main challenges currently faced. We propose the use of silicon photonics (SiPho) towards advancing interconnect throughput, socket connectivity and energy efficiency in MSB layouts, enabling a flat-topology wavelength division multiplexing (WDM)-based point-to-point (p2p) optical MSB interconnect scheme. We demonstrate WDM SiPho transceivers (TxRxs) co-assembled with their electronic circuits for up to 50 Gb/s line rate and 400 Gb/s aggregate data transmission and SiPho arrayed waveguide grating routers that can offer collision-less time of flight connectivity for up to 16 nodes. The capacity can scale to 2.8 Gb/s for an eight-socket MSB, when line rate scales to 50 Gb/s, yielding up to 69% energy reduction compared with the QuickPath Interconnect and highlighting the feasibility of single-hop p2p interconnects in MSB systems with >4 sockets

Towards maximum energy efficiency of carrier-injection-based silicon photonics

We present carrier-injection-based photonic switches, engineered for optical pulse distribution with maximum energy efficiency. We apply small-signal analysis and for the first time large-signal modelling to methodically optimize the switches for minimum energy consumption and to classify the electronic contributions from resistance, capacitance, and diode. We present optimized electronic switch activation, which yields a sixfold reduction in energy consumption and we show how static power consumption becomes a negligible factor for optical pulse switching. We demonstrate that with adjusted phase shifter dimensions, MZI-based switches can operate with additional 50% enhanced energy efficiency with down to 4 pJ per switching operation. We show even further efficiency improvement using ring-based designs, allowing an additional improvement of 50% in energy efficiency and we discuss the trade-off between efficiency and optical bandwidth associated to the Q-factor. We benchmark carrier-injection-based switches together with comparable technologies of the silicon photonics platform and identify carrier-injection to be the most suitable technology for pulse switching applications