A performance comparison of several superscalar processsor [sic] models with a VLIW processor

Superscalar and VLIW processors can both execute multiple instructions each cycle. Each employs a different instruction scheduling method to achieve multiple instruction execution. Superscalar processors schedule instructions dynamically, and VLIW processors execute statically scheduled instructions. This paper quantitatively compares various superscalar processor architectures with a Very Long Instruction Word architecture developed at the University of California, Irvine. An architectural overview and performance analysis of the superscalar processor models and VIPER, a VLIW processor designed to take advantage of the parallelizing capabilities of Percolation Scheduling, are presented. The motivation for this comparison is to study the capability of a dynamically scheduled processor to obtain the same performance achieved by a statically scheduled processor, and examine the hardware resources required by each

Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators

We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between -1 and 1 after each convolutional layer, and this leaves one bit unused in half-precision floating-point representation. By taking advantage of the unused bit, we create a backup for the most significant bit to protect it against the soft errors. Also, considering the fact that in MLC STT-RAMs the cost of memory operations (read and write), and reliability of a cell are content-dependent (some patterns take larger current and longer time, while they are more susceptible to soft error), we rearrange the data block to minimize the number of costly bit patterns. Combining these two techniques provides the same level of accuracy compared to an error-free baseline while improving the read and write energy by 9% and 6%, respectively

Enumeration and Asymptotic Formulas for Rectangular Partitions of the Hypercube

We study a two-parameter generalization of the Catalan numbers: $C_{d,p}(n)$ is the number of ways to subdivide the $d$-dimensional hypercube into $n$ rectangular blocks using orthogonal partitions of fixed arity $p$. Bremner \& Dotsenko introduced $C_{d,p}(n)$ in their work on Boardman--Vogt tensor products of operads; they used homological algebra to prove a recursive formula and a functional equation. We express $C_{d,p}(n)$ as simple finite sums, and determine their growth rate and asymptotic behaviour. We give an elementary proof of the functional equation, using a bijection between hypercube decompositions and a family of full $p$-ary trees. Our results generalize the well-known correspondence between Catalan numbers and full binary trees

Helicobacter pylori infection and insulin resistance in diabetic and nondiabetic population

Helicobacter pylori (HP) is a common worldwide infection with known gastrointestinal and nongastrointestinal complications. One of the gastrointestinal side effects posed for this organism is its role in diabetes and increased insulin resistance. The aim of this study was to evaluate the association between HP and insulin resistance in type 2 diabetic patients and nondiabetics. This cross-sectional study was carried out from May to December 2013 on 211 diabetic patients referred to diabetes clinic of Shahid Beheshti Hospital of Qom and 218 patients without diabetes. HP was evaluated using serology method and insulin resistance was calculated using HOMA-IR. The prevalence of H. pylori infection was 55.8% and 44.2% in diabetics and nondiabetics (P=0.001). The study population was divided into two HP positive and negative groups. Among nondiabetics, insulin resistance degree was 3.01±2.12 and 2.74±2.18 in HP+ and HP- patients, respectively P=0.704. Oppositely, insulin resistance was significantly higher in diabetic HP+ patients rather than seronegative ones (4.484±2.781 versus 3.160±2.327, P=0.013). In diabetic patients, in addition to higher prevalence of HP, it causes a higher degree of insulin resistance. © 2014 Jamshid Vafaeimanesh et al

VIPER : a 25-MHz, 100-MIPS peak VLIW micro-processor

This paper describes the design and implementation of a very long instruction word (VLIW) microprocessor. The VIPER (VLIW integer processor) contains four pipelined functional units, and can achieve 100 MIPS peak performance at 25 MHz. The procesor is capable of performing multiway branch operations, two load/store operations and up to four ALU operations in each clock cycle, with full register file access to each functional unit. VIPER is the first VLIW microprocessor known that can achieve this level of performance. Designed in twelve months, the processor is integrated with an instruction cache controller and a data cache, requiring 450,000 transistors and a die size of 12.9 by 9.1 mm in a 1.2 µm technology